1/*
2 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
3 *
4 * (C) Copyright 2015, Xilinx, Inc.
5 *
6 * Michal Simek <michal.simek@xilinx.com>
7 *
8 * SPDX-License-Identifier:	GPL-2.0+
9 */
10
11/dts-v1/;
12
13#include "zynqmp.dtsi"
14#include "zynqmp-clk.dtsi"
15
16/ {
17	model = "ZynqMP zc1751-xm015-dc1 RevA";
18	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
19
20	aliases {
21		ethernet0 = &gem3;
22		gpio0 = &gpio;
23		i2c0 = &i2c1;
24		mmc0 = &sdhci0;
25		mmc1 = &sdhci1;
26		rtc0 = &rtc;
27		serial0 = &uart0;
28		spi0 = &qspi;
29		usb0 = &usb0;
30	};
31
32	chosen {
33		bootargs = "earlycon";
34		stdout-path = "serial0:115200n8";
35	};
36
37	memory@0 {
38		device_type = "memory";
39		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
40	};
41};
42
43/* fpd_dma clk 667MHz, lpd_dma 500MHz */
44&fpd_dma_chan1 {
45	status = "okay";
46	xlnx,include-sg; /* for testing purpose */
47	xlnx,overfetch; /* for testing purpose */
48	xlnx,ratectrl = <0>; /* for testing purpose */
49	xlnx,src-issue = <31>;
50};
51
52&fpd_dma_chan2 {
53	status = "okay";
54	xlnx,ratectrl = <100>; /* for testing purpose */
55	xlnx,src-issue = <4>; /* for testing purpose */
56};
57
58&fpd_dma_chan3 {
59	status = "okay";
60};
61
62&fpd_dma_chan4 {
63	status = "okay";
64	xlnx,include-sg; /* for testing purpose */
65};
66
67&fpd_dma_chan5 {
68	status = "okay";
69};
70
71&fpd_dma_chan6 {
72	status = "okay";
73	xlnx,include-sg; /* for testing purpose */
74};
75
76&fpd_dma_chan7 {
77	status = "okay";
78};
79
80&fpd_dma_chan8 {
81	status = "okay";
82	xlnx,include-sg; /* for testing purpose */
83};
84
85&gem3 {
86	status = "okay";
87	local-mac-address = [00 0a 35 00 02 90];
88	phy-handle = <&phy0>;
89	phy-mode = "rgmii-id";
90	phy0: phy@0 {
91		reg = <0>;
92	};
93};
94
95&gpio {
96	status = "okay";
97};
98
99&gpu {
100	status = "okay";
101};
102
103&i2c1 {
104	status = "okay";
105	clock-frequency = <400000>;
106	eeprom@55 {
107		compatible = "at,24c64"; /* 24AA64 */
108		reg = <0x55>;
109	};
110};
111
112&qspi {
113	status = "okay";
114	flash@0 {
115		compatible = "m25p80"; /* Micron MT25QU512ABB8ESF */
116		#address-cells = <1>;
117		#size-cells = <1>;
118		reg = <0x0>;
119		spi-tx-bus-width = <1>;
120		spi-rx-bus-width = <4>;
121		spi-max-frequency = <108000000>; /* Based on DC1 spec */
122		partition@qspi-fsbl-uboot { /* for testing purpose */
123			label = "qspi-fsbl-uboot";
124			reg = <0x0 0x100000>;
125		};
126		partition@qspi-linux { /* for testing purpose */
127			label = "qspi-linux";
128			reg = <0x100000 0x500000>;
129		};
130		partition@qspi-device-tree { /* for testing purpose */
131			label = "qspi-device-tree";
132			reg = <0x600000 0x20000>;
133		};
134		partition@qspi-rootfs { /* for testing purpose */
135			label = "qspi-rootfs";
136			reg = <0x620000 0x5E0000>;
137		};
138	};
139};
140
141&rtc {
142	status = "okay";
143};
144
145&sata {
146	status = "okay";
147	/* SATA phy OOB timing settings */
148	ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
149	ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
150	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
151	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
152	ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
153	ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
154	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
155	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
156};
157
158/* eMMC */
159&sdhci0 {
160	status = "okay";
161	bus-width = <8>;
162	xlnx,mio_bank = <0>;
163};
164
165/* SD1 with level shifter */
166&sdhci1 {
167	status = "okay";
168	no-1-8-v;       /* for 1.0 silicon */
169	xlnx,mio_bank = <1>;
170};
171
172&uart0 {
173	status = "okay";
174};
175
176/* ULPI SMSC USB3320 */
177&usb0 {
178	status = "okay";
179	dr_mode = "host";
180};
181
182&xilinx_drm {
183	status = "okay";
184};
185
186&xlnx_dp {
187	status = "okay";
188};
189
190&xlnx_dp_sub {
191	status = "okay";
192	xlnx,vid-clk-pl;
193};
194
195&xlnx_dp_snd_pcm0 {
196	status = "okay";
197};
198
199&xlnx_dp_snd_pcm1 {
200	status = "okay";
201};
202
203&xlnx_dp_snd_card {
204	status = "okay";
205};
206
207&xlnx_dp_snd_codec0 {
208	status = "okay";
209};
210
211&xlnx_dpdma {
212	status = "okay";
213};
214