1*ee97a999SMichal Simek// SPDX-License-Identifier: GPL-2.0+ 2*ee97a999SMichal Simek/* 3*ee97a999SMichal Simek * dts file for Xilinx ZynqMP Mini Configuration 4*ee97a999SMichal Simek * 5*ee97a999SMichal Simek * (C) Copyright 2017, Xilinx, Inc. 6*ee97a999SMichal Simek * 7*ee97a999SMichal Simek * Michal Simek <michal.simek@xilinx.com> 8*ee97a999SMichal Simek */ 9*ee97a999SMichal Simek 10*ee97a999SMichal Simek/dts-v1/; 11*ee97a999SMichal Simek 12*ee97a999SMichal Simek/ { 13*ee97a999SMichal Simek model = "ZynqMP MINI"; 14*ee97a999SMichal Simek compatible = "xlnx,zynqmp"; 15*ee97a999SMichal Simek #address-cells = <2>; 16*ee97a999SMichal Simek #size-cells = <2>; 17*ee97a999SMichal Simek 18*ee97a999SMichal Simek aliases { 19*ee97a999SMichal Simek serial0 = &dcc; 20*ee97a999SMichal Simek }; 21*ee97a999SMichal Simek 22*ee97a999SMichal Simek chosen { 23*ee97a999SMichal Simek stdout-path = "serial0:115200n8"; 24*ee97a999SMichal Simek }; 25*ee97a999SMichal Simek 26*ee97a999SMichal Simek memory@0 { 27*ee97a999SMichal Simek device_type = "memory"; 28*ee97a999SMichal Simek reg = <0x0 0xfffc0000 0x0 0x40000>, <0x0 0x0 0x0 0x80000000>; 29*ee97a999SMichal Simek }; 30*ee97a999SMichal Simek 31*ee97a999SMichal Simek dcc: dcc { 32*ee97a999SMichal Simek compatible = "arm,dcc"; 33*ee97a999SMichal Simek status = "disabled"; 34*ee97a999SMichal Simek u-boot,dm-pre-reloc; 35*ee97a999SMichal Simek }; 36*ee97a999SMichal Simek}; 37*ee97a999SMichal Simek 38*ee97a999SMichal Simek&dcc { 39*ee97a999SMichal Simek status = "okay"; 40*ee97a999SMichal Simek}; 41