1bc0f4ed1SSiva Durga Prasad Paladugu// SPDX-License-Identifier: GPL-2.0+ 2bc0f4ed1SSiva Durga Prasad Paladugu/* 3bc0f4ed1SSiva Durga Prasad Paladugu * dts file for Xilinx ZynqMP Mini Configuration 4bc0f4ed1SSiva Durga Prasad Paladugu * 5bc0f4ed1SSiva Durga Prasad Paladugu * (C) Copyright 2018, Xilinx, Inc. 6bc0f4ed1SSiva Durga Prasad Paladugu * 7bc0f4ed1SSiva Durga Prasad Paladugu * Siva Durga Prasad <siva.durga.paladugu@xilinx.com> 8bc0f4ed1SSiva Durga Prasad Paladugu */ 9bc0f4ed1SSiva Durga Prasad Paladugu 10bc0f4ed1SSiva Durga Prasad Paladugu/dts-v1/; 11bc0f4ed1SSiva Durga Prasad Paladugu 12bc0f4ed1SSiva Durga Prasad Paladugu/ { 13*f3289d1fSMichal Simek model = "ZynqMP MINI EMMC1"; 14bc0f4ed1SSiva Durga Prasad Paladugu compatible = "xlnx,zynqmp"; 15bc0f4ed1SSiva Durga Prasad Paladugu #address-cells = <2>; 16bc0f4ed1SSiva Durga Prasad Paladugu #size-cells = <2>; 17bc0f4ed1SSiva Durga Prasad Paladugu 18bc0f4ed1SSiva Durga Prasad Paladugu aliases { 19bc0f4ed1SSiva Durga Prasad Paladugu serial0 = &dcc; 20bc0f4ed1SSiva Durga Prasad Paladugu mmc0 = &sdhci1; 21bc0f4ed1SSiva Durga Prasad Paladugu }; 22bc0f4ed1SSiva Durga Prasad Paladugu 23bc0f4ed1SSiva Durga Prasad Paladugu chosen { 24bc0f4ed1SSiva Durga Prasad Paladugu stdout-path = "serial0:115200n8"; 25bc0f4ed1SSiva Durga Prasad Paladugu }; 26bc0f4ed1SSiva Durga Prasad Paladugu 27bc0f4ed1SSiva Durga Prasad Paladugu memory@0 { 28bc0f4ed1SSiva Durga Prasad Paladugu device_type = "memory"; 29bc0f4ed1SSiva Durga Prasad Paladugu reg = <0x0 0x0 0x0 0x20000000>; 30bc0f4ed1SSiva Durga Prasad Paladugu }; 31bc0f4ed1SSiva Durga Prasad Paladugu 32bc0f4ed1SSiva Durga Prasad Paladugu dcc: dcc { 33bc0f4ed1SSiva Durga Prasad Paladugu compatible = "arm,dcc"; 34bc0f4ed1SSiva Durga Prasad Paladugu status = "disabled"; 35bc0f4ed1SSiva Durga Prasad Paladugu u-boot,dm-pre-reloc; 36bc0f4ed1SSiva Durga Prasad Paladugu }; 37bc0f4ed1SSiva Durga Prasad Paladugu 38bc0f4ed1SSiva Durga Prasad Paladugu clk_xin: clk_xin { 39bc0f4ed1SSiva Durga Prasad Paladugu compatible = "fixed-clock"; 40bc0f4ed1SSiva Durga Prasad Paladugu #clock-cells = <0>; 41bc0f4ed1SSiva Durga Prasad Paladugu clock-frequency = <200000000>; 42bc0f4ed1SSiva Durga Prasad Paladugu }; 43bc0f4ed1SSiva Durga Prasad Paladugu 44bc0f4ed1SSiva Durga Prasad Paladugu amba: amba { 45bc0f4ed1SSiva Durga Prasad Paladugu compatible = "simple-bus"; 46bc0f4ed1SSiva Durga Prasad Paladugu #address-cells = <2>; 47bc0f4ed1SSiva Durga Prasad Paladugu #size-cells = <2>; 48bc0f4ed1SSiva Durga Prasad Paladugu ranges; 49bc0f4ed1SSiva Durga Prasad Paladugu 50bc0f4ed1SSiva Durga Prasad Paladugu sdhci1: sdhci@ff170000 { 51bc0f4ed1SSiva Durga Prasad Paladugu u-boot,dm-pre-reloc; 52bc0f4ed1SSiva Durga Prasad Paladugu compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 53bc0f4ed1SSiva Durga Prasad Paladugu status = "disabled"; 54bc0f4ed1SSiva Durga Prasad Paladugu reg = <0x0 0xff170000 0x0 0x1000>; 5592226b5aSMichal Simek clock-names = "clk_xin", "clk_ahb"; 5692226b5aSMichal Simek clocks = <&clk_xin &clk_xin>; 57bc0f4ed1SSiva Durga Prasad Paladugu xlnx,device_id = <1>; 58bc0f4ed1SSiva Durga Prasad Paladugu }; 59bc0f4ed1SSiva Durga Prasad Paladugu }; 60bc0f4ed1SSiva Durga Prasad Paladugu}; 61bc0f4ed1SSiva Durga Prasad Paladugu 62bc0f4ed1SSiva Durga Prasad Paladugu&dcc { 63bc0f4ed1SSiva Durga Prasad Paladugu status = "okay"; 64bc0f4ed1SSiva Durga Prasad Paladugu}; 65bc0f4ed1SSiva Durga Prasad Paladugu 66bc0f4ed1SSiva Durga Prasad Paladugu&sdhci1 { 67bc0f4ed1SSiva Durga Prasad Paladugu status = "okay"; 68bc0f4ed1SSiva Durga Prasad Paladugu}; 69