xref: /openbmc/u-boot/arch/arm/dts/zynqmp-clk-ccf.dtsi (revision ebce73f0afe6efe926328c10316e54f3e43a33a1) 
1/*
2 * Clock specification for Xilinx ZynqMP
3 *
4 * (C) Copyright 2017, Xilinx, Inc.
5 *
6 * Michal Simek <michal.simek@xilinx.com>
7 *
8 * SPDX-License-Identifier:     GPL-2.0+
9 */
10
11/ {
12	fclk0: fclk0 {
13		status = "disabled";
14		compatible = "xlnx,fclk";
15		clocks = <&clkc 71>;
16	};
17
18	fclk1: fclk1 {
19		status = "disabled";
20		compatible = "xlnx,fclk";
21		clocks = <&clkc 72>;
22	};
23
24	fclk2: fclk2 {
25		status = "disabled";
26		compatible = "xlnx,fclk";
27		clocks = <&clkc 73>;
28	};
29
30	fclk3: fclk3 {
31		status = "disabled";
32		compatible = "xlnx,fclk";
33		clocks = <&clkc 74>;
34	};
35
36	pss_ref_clk: pss_ref_clk {
37		u-boot,dm-pre-reloc;
38		compatible = "fixed-clock";
39		#clock-cells = <0>;
40		clock-frequency = <33333333>;
41	};
42
43	video_clk: video_clk {
44		u-boot,dm-pre-reloc;
45		compatible = "fixed-clock";
46		#clock-cells = <0>;
47		clock-frequency = <27000000>;
48	};
49
50	pss_alt_ref_clk: pss_alt_ref_clk {
51		u-boot,dm-pre-reloc;
52		compatible = "fixed-clock";
53		#clock-cells = <0>;
54		clock-frequency = <0>;
55	};
56
57	gt_crx_ref_clk: gt_crx_ref_clk {
58		u-boot,dm-pre-reloc;
59		compatible = "fixed-clock";
60		#clock-cells = <0>;
61		clock-frequency = <108000000>;
62	};
63
64	aux_ref_clk: aux_ref_clk {
65		u-boot,dm-pre-reloc;
66		compatible = "fixed-clock";
67		#clock-cells = <0>;
68		clock-frequency = <27000000>;
69	};
70
71	clkc: clkc {
72		u-boot,dm-pre-reloc;
73		#clock-cells = <1>;
74		compatible = "xlnx,zynqmp-clkc";
75		clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;
76		clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk";
77		clock-output-names = "iopll", "rpll", "apll", "dpll",
78				"vpll", "iopll_to_fpd", "rpll_to_fpd",
79				"apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd",
80				"acpu", "acpu_half", "dbf_fpd", "dbf_lpd",
81				"dbg_trace", "dbg_tstmp", "dp_video_ref",
82				"dp_audio_ref", "dp_stc_ref", "gdma_ref",
83				"dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref",
84				"gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref",
85				"topsw_main", "topsw_lsbus", "gtgref0_ref",
86				"lpd_switch", "lpd_lsbus", "usb0_bus_ref",
87				"usb1_bus_ref", "usb3_dual_ref", "usb0",
88				"usb1", "cpu_r5", "cpu_r5_core", "csu_spb",
89				"csu_pll", "pcap", "iou_switch", "gem_tsu_ref",
90				"gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref",
91				"gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx",
92				"gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref",
93				"uart0_ref", "uart1_ref", "spi0_ref",
94				"spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref",
95				"can0_ref", "can1_ref", "can0", "can1",
96				"dll_ref", "adma_ref", "timestamp_ref",
97				"ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt";
98	};
99
100	dp_aclk: dp_aclk {
101		compatible = "fixed-clock";
102		#clock-cells = <0>;
103		clock-frequency = <100000000>;
104		clock-accuracy = <100>;
105	};
106};
107
108&can0 {
109	clocks = <&clkc 63>, <&clkc 31>;
110};
111
112&can1 {
113	clocks = <&clkc 64>, <&clkc 31>;
114};
115
116&cpu0 {
117	clocks = <&clkc 10>;
118};
119
120&fpd_dma_chan1 {
121	clocks = <&clkc 19>, <&clkc 31>;
122};
123
124&fpd_dma_chan2 {
125	clocks = <&clkc 19>, <&clkc 31>;
126};
127
128&fpd_dma_chan3 {
129	clocks = <&clkc 19>, <&clkc 31>;
130};
131
132&fpd_dma_chan4 {
133	clocks = <&clkc 19>, <&clkc 31>;
134};
135
136&fpd_dma_chan5 {
137	clocks = <&clkc 19>, <&clkc 31>;
138};
139
140&fpd_dma_chan6 {
141	clocks = <&clkc 19>, <&clkc 31>;
142};
143
144&fpd_dma_chan7 {
145	clocks = <&clkc 19>, <&clkc 31>;
146};
147
148&fpd_dma_chan8 {
149	clocks = <&clkc 19>, <&clkc 31>;
150};
151
152&gpu {
153	clocks = <&clkc 24>, <&clkc 25>, <&clkc 26>;
154};
155
156&lpd_dma_chan1 {
157	clocks = <&clkc 68>, <&clkc 31>;
158};
159
160&lpd_dma_chan2 {
161	clocks = <&clkc 68>, <&clkc 31>;
162};
163
164&lpd_dma_chan3 {
165	clocks = <&clkc 68>, <&clkc 31>;
166};
167
168&lpd_dma_chan4 {
169	clocks = <&clkc 68>, <&clkc 31>;
170};
171
172&lpd_dma_chan5 {
173	clocks = <&clkc 68>, <&clkc 31>;
174};
175
176&lpd_dma_chan6 {
177	clocks = <&clkc 68>, <&clkc 31>;
178};
179
180&lpd_dma_chan7 {
181	clocks = <&clkc 68>, <&clkc 31>;
182};
183
184&lpd_dma_chan8 {
185	clocks = <&clkc 68>, <&clkc 31>;
186};
187
188&nand0 {
189	clocks = <&clkc 60>, <&clkc 31>;
190};
191
192&gem0 {
193	clocks = <&clkc 31>, <&clkc 49>, <&clkc 45>, <&clkc 49>, <&clkc 44>;
194	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
195};
196
197&gem1 {
198	clocks = <&clkc 31>, <&clkc 50>, <&clkc 46>, <&clkc 50>, <&clkc 44>;
199	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
200};
201
202&gem2 {
203	clocks = <&clkc 31>, <&clkc 51>, <&clkc 47>, <&clkc 51>, <&clkc 44>;
204	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
205};
206
207&gem3 {
208	clocks = <&clkc 31>, <&clkc 52>, <&clkc 48>, <&clkc 52>, <&clkc 44>;
209	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
210};
211
212&gpio {
213	clocks = <&clkc 31>;
214};
215
216&i2c0 {
217	clocks = <&clkc 61>;
218};
219
220&i2c1 {
221	clocks = <&clkc 62>;
222};
223
224&pcie {
225	clocks = <&clkc 23>;
226};
227
228&qspi {
229	clocks = <&clkc 53>, <&clkc 31>;
230};
231
232&sata {
233	clocks = <&clkc 22>;
234};
235
236&sdhci0 {
237	clocks = <&clkc 54>, <&clkc 31>;
238};
239
240&sdhci1 {
241	clocks = <&clkc 55>, <&clkc 31>;
242};
243
244&spi0 {
245	clocks = <&clkc 58>, <&clkc 31>;
246};
247
248&spi1 {
249	clocks = <&clkc 59>, <&clkc 31>;
250};
251
252&uart0 {
253	clocks = <&clkc 56>,  <&clkc 31>;
254};
255
256&uart1 {
257	clocks = <&clkc 57>,  <&clkc 31>;
258};
259
260&usb0 {
261	clocks = <&clkc 32>,  <&clkc 34>;
262};
263
264&usb1 {
265	clocks = <&clkc 33>,  <&clkc 34>;
266};
267
268&watchdog0 {
269	clocks = <&clkc 75>;
270};
271
272&xilinx_ams {
273	clocks = <&clkc 70>;
274};
275
276&xilinx_drm {
277	clocks = <&clkc 16>;
278};
279
280&xlnx_dp {
281	clocks = <&dp_aclk>, <&clkc 17>;
282};
283
284&xlnx_dpdma {
285	clocks = <&clkc 20>;
286};
287
288&xlnx_dp_snd_codec0 {
289	clocks = <&clkc 17>;
290};
291