1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Clock specification for Xilinx ZynqMP
4 *
5 * (C) Copyright 2017, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/ {
11	fclk0: fclk0 {
12		status = "disabled";
13		compatible = "xlnx,fclk";
14		clocks = <&clkc 71>;
15	};
16
17	fclk1: fclk1 {
18		status = "disabled";
19		compatible = "xlnx,fclk";
20		clocks = <&clkc 72>;
21	};
22
23	fclk2: fclk2 {
24		status = "disabled";
25		compatible = "xlnx,fclk";
26		clocks = <&clkc 73>;
27	};
28
29	fclk3: fclk3 {
30		status = "disabled";
31		compatible = "xlnx,fclk";
32		clocks = <&clkc 74>;
33	};
34
35	pss_ref_clk: pss_ref_clk {
36		u-boot,dm-pre-reloc;
37		compatible = "fixed-clock";
38		#clock-cells = <0>;
39		clock-frequency = <33333333>;
40	};
41
42	video_clk: video_clk {
43		u-boot,dm-pre-reloc;
44		compatible = "fixed-clock";
45		#clock-cells = <0>;
46		clock-frequency = <27000000>;
47	};
48
49	pss_alt_ref_clk: pss_alt_ref_clk {
50		u-boot,dm-pre-reloc;
51		compatible = "fixed-clock";
52		#clock-cells = <0>;
53		clock-frequency = <0>;
54	};
55
56	gt_crx_ref_clk: gt_crx_ref_clk {
57		u-boot,dm-pre-reloc;
58		compatible = "fixed-clock";
59		#clock-cells = <0>;
60		clock-frequency = <108000000>;
61	};
62
63	aux_ref_clk: aux_ref_clk {
64		u-boot,dm-pre-reloc;
65		compatible = "fixed-clock";
66		#clock-cells = <0>;
67		clock-frequency = <27000000>;
68	};
69
70	clkc: clkc {
71		u-boot,dm-pre-reloc;
72		#clock-cells = <1>;
73		compatible = "xlnx,zynqmp-clkc";
74		clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;
75		clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk";
76		clock-output-names = "iopll", "rpll", "apll", "dpll",
77				"vpll", "iopll_to_fpd", "rpll_to_fpd",
78				"apll_to_lpd", "dpll_to_lpd", "vpll_to_lpd",
79				"acpu", "acpu_half", "dbf_fpd", "dbf_lpd",
80				"dbg_trace", "dbg_tstmp", "dp_video_ref",
81				"dp_audio_ref", "dp_stc_ref", "gdma_ref",
82				"dpdma_ref", "ddr_ref", "sata_ref", "pcie_ref",
83				"gpu_ref", "gpu_pp0_ref", "gpu_pp1_ref",
84				"topsw_main", "topsw_lsbus", "gtgref0_ref",
85				"lpd_switch", "lpd_lsbus", "usb0_bus_ref",
86				"usb1_bus_ref", "usb3_dual_ref", "usb0",
87				"usb1", "cpu_r5", "cpu_r5_core", "csu_spb",
88				"csu_pll", "pcap", "iou_switch", "gem_tsu_ref",
89				"gem_tsu", "gem0_ref", "gem1_ref", "gem2_ref",
90				"gem3_ref", "gem0_tx", "gem1_tx", "gem2_tx",
91				"gem3_tx", "qspi_ref", "sdio0_ref", "sdio1_ref",
92				"uart0_ref", "uart1_ref", "spi0_ref",
93				"spi1_ref", "nand_ref", "i2c0_ref", "i2c1_ref",
94				"can0_ref", "can1_ref", "can0", "can1",
95				"dll_ref", "adma_ref", "timestamp_ref",
96				"ams_ref", "pl0", "pl1", "pl2", "pl3", "wdt";
97	};
98
99	dp_aclk: dp_aclk {
100		compatible = "fixed-clock";
101		#clock-cells = <0>;
102		clock-frequency = <100000000>;
103		clock-accuracy = <100>;
104	};
105};
106
107&can0 {
108	clocks = <&clkc 63>, <&clkc 31>;
109};
110
111&can1 {
112	clocks = <&clkc 64>, <&clkc 31>;
113};
114
115&cpu0 {
116	clocks = <&clkc 10>;
117};
118
119&fpd_dma_chan1 {
120	clocks = <&clkc 19>, <&clkc 31>;
121};
122
123&fpd_dma_chan2 {
124	clocks = <&clkc 19>, <&clkc 31>;
125};
126
127&fpd_dma_chan3 {
128	clocks = <&clkc 19>, <&clkc 31>;
129};
130
131&fpd_dma_chan4 {
132	clocks = <&clkc 19>, <&clkc 31>;
133};
134
135&fpd_dma_chan5 {
136	clocks = <&clkc 19>, <&clkc 31>;
137};
138
139&fpd_dma_chan6 {
140	clocks = <&clkc 19>, <&clkc 31>;
141};
142
143&fpd_dma_chan7 {
144	clocks = <&clkc 19>, <&clkc 31>;
145};
146
147&fpd_dma_chan8 {
148	clocks = <&clkc 19>, <&clkc 31>;
149};
150
151&gpu {
152	clocks = <&clkc 24>, <&clkc 25>, <&clkc 26>;
153};
154
155&lpd_dma_chan1 {
156	clocks = <&clkc 68>, <&clkc 31>;
157};
158
159&lpd_dma_chan2 {
160	clocks = <&clkc 68>, <&clkc 31>;
161};
162
163&lpd_dma_chan3 {
164	clocks = <&clkc 68>, <&clkc 31>;
165};
166
167&lpd_dma_chan4 {
168	clocks = <&clkc 68>, <&clkc 31>;
169};
170
171&lpd_dma_chan5 {
172	clocks = <&clkc 68>, <&clkc 31>;
173};
174
175&lpd_dma_chan6 {
176	clocks = <&clkc 68>, <&clkc 31>;
177};
178
179&lpd_dma_chan7 {
180	clocks = <&clkc 68>, <&clkc 31>;
181};
182
183&lpd_dma_chan8 {
184	clocks = <&clkc 68>, <&clkc 31>;
185};
186
187&nand0 {
188	clocks = <&clkc 60>, <&clkc 31>;
189};
190
191&gem0 {
192	clocks = <&clkc 31>, <&clkc 49>, <&clkc 45>, <&clkc 49>, <&clkc 44>;
193	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
194};
195
196&gem1 {
197	clocks = <&clkc 31>, <&clkc 50>, <&clkc 46>, <&clkc 50>, <&clkc 44>;
198	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
199};
200
201&gem2 {
202	clocks = <&clkc 31>, <&clkc 51>, <&clkc 47>, <&clkc 51>, <&clkc 44>;
203	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
204};
205
206&gem3 {
207	clocks = <&clkc 31>, <&clkc 52>, <&clkc 48>, <&clkc 52>, <&clkc 44>;
208	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
209};
210
211&gpio {
212	clocks = <&clkc 31>;
213};
214
215&i2c0 {
216	clocks = <&clkc 61>;
217};
218
219&i2c1 {
220	clocks = <&clkc 62>;
221};
222
223&pcie {
224	clocks = <&clkc 23>;
225};
226
227&qspi {
228	clocks = <&clkc 53>, <&clkc 31>;
229};
230
231&sata {
232	clocks = <&clkc 22>;
233};
234
235&sdhci0 {
236	clocks = <&clkc 54>, <&clkc 31>;
237};
238
239&sdhci1 {
240	clocks = <&clkc 55>, <&clkc 31>;
241};
242
243&spi0 {
244	clocks = <&clkc 58>, <&clkc 31>;
245};
246
247&spi1 {
248	clocks = <&clkc 59>, <&clkc 31>;
249};
250
251&uart0 {
252	clocks = <&clkc 56>,  <&clkc 31>;
253};
254
255&uart1 {
256	clocks = <&clkc 57>,  <&clkc 31>;
257};
258
259&usb0 {
260	clocks = <&clkc 32>,  <&clkc 34>;
261};
262
263&usb1 {
264	clocks = <&clkc 33>,  <&clkc 34>;
265};
266
267&watchdog0 {
268	clocks = <&clkc 75>;
269};
270
271&xilinx_ams {
272	clocks = <&clkc 70>;
273};
274
275&xilinx_drm {
276	clocks = <&clkc 16>;
277};
278
279&xlnx_dp {
280	clocks = <&dp_aclk>, <&clkc 17>;
281};
282
283&xlnx_dpdma {
284	clocks = <&clkc 20>;
285};
286
287&xlnx_dp_snd_codec0 {
288	clocks = <&clkc 17>;
289};
290