xref: /openbmc/u-boot/arch/arm/dts/zynq-zturn.dts (revision f77d4410) 
1// SPDX-License-Identifier: GPL-2.0
2/*
3 *  Copyright (C) 2015 Andrea Merello <adnrea.merello@gmail.com>
4 *  Copyright (C) 2017 Alexander Graf <agraf@suse.de>
5 *
6 *  Based on zynq-zed.dts which is:
7 *  Copyright (C) 2011 - 2014 Xilinx
8 *  Copyright (C) 2012 National Instruments Corp.
9 *
10 */
11
12/dts-v1/;
13/include/ "zynq-7000.dtsi"
14
15/ {
16	model = "Zynq Z-Turn MYIR Board";
17	compatible = "myir,zynq-zturn", "xlnx,zynq-7000";
18
19	aliases {
20		ethernet0 = &gem0;
21		serial0 = &uart1;
22		serial1 = &uart0;
23		mmc0 = &sdhci0;
24	};
25
26	memory@0 {
27		device_type = "memory";
28		reg = <0x0 0x40000000>;
29	};
30
31	chosen {
32		stdout-path = "serial0:115200n8";
33	};
34
35	gpio-leds {
36		compatible = "gpio-leds";
37		usr-led1 {
38			label = "usr-led1";
39			gpios = <&gpio0 0x0 0x1>;
40			default-state = "off";
41		};
42
43		usr-led2 {
44			label = "usr-led2";
45			gpios = <&gpio0 0x9 0x1>;
46			default-state = "off";
47		};
48	};
49
50	gpio-keys {
51		compatible = "gpio-keys";
52		autorepeat;
53		K1 {
54			label = "K1";
55			gpios = <&gpio0 0x32 0x1>;
56			linux,code = <0x66>;
57			gpio-key,wakeup;
58			autorepeat;
59		};
60	};
61};
62
63&clkc {
64	ps-clk-frequency = <33333333>;
65};
66
67&qspi {
68	u-boot,dm-pre-reloc;
69	status = "okay";
70};
71
72&gem0 {
73	status = "okay";
74	phy-mode = "rgmii-id";
75	phy-handle = <&ethernet_phy>;
76
77	ethernet_phy: ethernet-phy@0 {
78		reg = <0x0>;
79	};
80};
81
82&sdhci0 {
83	u-boot,dm-pre-reloc;
84	status = "okay";
85};
86
87&uart0 {
88	u-boot,dm-pre-reloc;
89	status = "okay";
90};
91
92&uart1 {
93	u-boot,dm-pre-reloc;
94	status = "okay";
95};
96
97&usb0 {
98	status = "okay";
99	dr_mode = "host";
100};
101
102&can0 {
103	status = "okay";
104};
105
106&i2c0 {
107	status = "okay";
108	clock-frequency = <400000>;
109
110	stlm75@49 {
111		status = "okay";
112		compatible = "lm75";
113		reg = <0x49>;
114	};
115
116	accelerometer@53 {
117		compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x";
118		reg = <0x53>;
119		interrupt-parent = <&intc>;
120		interrupts = <0x0 0x1e 0x4>;
121	};
122};
123