xref: /openbmc/u-boot/arch/arm/dts/zynq-zc706.dts (revision c0982871) 
1/*
2 * Xilinx ZC706 board DTS
3 *
4 *  Copyright (C) 2011 - 2015 Xilinx
5 *  Copyright (C) 2012 National Instruments Corp.
6 *
7 * SPDX-License-Identifier:	GPL-2.0+
8 */
9/dts-v1/;
10#include "zynq-7000.dtsi"
11
12/ {
13	model = "Zynq ZC706 Development Board";
14	compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
15
16	aliases {
17		ethernet0 = &gem0;
18		i2c0 = &i2c0;
19		serial0 = &uart1;
20		spi0 = &qspi;
21	};
22
23	memory {
24		device_type = "memory";
25		reg = <0x0 0x40000000>;
26	};
27
28	chosen {
29		bootargs = "earlyprintk";
30		stdout-path = "serial0:115200n8";
31	};
32
33	usb_phy0: phy0 {
34		compatible = "usb-nop-xceiv";
35		#phy-cells = <0>;
36	};
37};
38
39&clkc {
40	ps-clk-frequency = <33333333>;
41};
42
43&gem0 {
44	status = "okay";
45	phy-mode = "rgmii-id";
46	phy-handle = <&ethernet_phy>;
47	pinctrl-names = "default";
48	pinctrl-0 = <&pinctrl_gem0_default>;
49
50	ethernet_phy: ethernet-phy@7 {
51		reg = <7>;
52	};
53};
54
55&gpio0 {
56	pinctrl-names = "default";
57	pinctrl-0 = <&pinctrl_gpio0_default>;
58};
59
60&i2c0 {
61	status = "okay";
62	clock-frequency = <400000>;
63	pinctrl-names = "default";
64	pinctrl-0 = <&pinctrl_i2c0_default>;
65
66	i2cswitch@74 {
67		compatible = "nxp,pca9548";
68		#address-cells = <1>;
69		#size-cells = <0>;
70		reg = <0x74>;
71
72		i2c@0 {
73			#address-cells = <1>;
74			#size-cells = <0>;
75			reg = <0>;
76			si570: clock-generator@5d {
77				#clock-cells = <0>;
78				compatible = "silabs,si570";
79				temperature-stability = <50>;
80				reg = <0x5d>;
81				factory-fout = <156250000>;
82				clock-frequency = <148500000>;
83			};
84		};
85
86		i2c@2 {
87			#address-cells = <1>;
88			#size-cells = <0>;
89			reg = <2>;
90			eeprom@54 {
91				compatible = "at,24c08";
92				reg = <0x54>;
93			};
94		};
95
96		i2c@3 {
97			#address-cells = <1>;
98			#size-cells = <0>;
99			reg = <3>;
100			gpio@21 {
101				compatible = "ti,tca6416";
102				reg = <0x21>;
103				gpio-controller;
104				#gpio-cells = <2>;
105			};
106		};
107
108		i2c@4 {
109			#address-cells = <1>;
110			#size-cells = <0>;
111			reg = <4>;
112			rtc@51 {
113				compatible = "nxp,pcf8563";
114				reg = <0x51>;
115			};
116		};
117
118		i2c@7 {
119			#address-cells = <1>;
120			#size-cells = <0>;
121			reg = <7>;
122			ucd90120@65 {
123				compatible = "ti,ucd90120";
124				reg = <0x65>;
125			};
126		};
127	};
128};
129
130&pinctrl0 {
131	pinctrl_gem0_default: gem0-default {
132		mux {
133			function = "ethernet0";
134			groups = "ethernet0_0_grp";
135		};
136
137		conf {
138			groups = "ethernet0_0_grp";
139			slew-rate = <0>;
140			io-standard = <4>;
141		};
142
143		conf-rx {
144			pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
145			bias-high-impedance;
146			low-power-disable;
147		};
148
149		conf-tx {
150			pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
151			low-power-enable;
152			bias-disable;
153		};
154
155		mux-mdio {
156			function = "mdio0";
157			groups = "mdio0_0_grp";
158		};
159
160		conf-mdio {
161			groups = "mdio0_0_grp";
162			slew-rate = <0>;
163			io-standard = <1>;
164			bias-disable;
165		};
166	};
167
168	pinctrl_gpio0_default: gpio0-default {
169		mux {
170			function = "gpio0";
171			groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp";
172		};
173
174		conf {
175			groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp";
176			slew-rate = <0>;
177			io-standard = <1>;
178		};
179
180		conf-pull-up {
181			pins = "MIO46", "MIO47";
182			bias-pull-up;
183		};
184
185		conf-pull-none {
186			pins = "MIO7";
187			bias-disable;
188		};
189	};
190
191	pinctrl_i2c0_default: i2c0-default {
192		mux {
193			groups = "i2c0_10_grp";
194			function = "i2c0";
195		};
196
197		conf {
198			groups = "i2c0_10_grp";
199			bias-pull-up;
200			slew-rate = <0>;
201			io-standard = <1>;
202		};
203	};
204
205	pinctrl_sdhci0_default: sdhci0-default {
206		mux {
207			groups = "sdio0_2_grp";
208			function = "sdio0";
209		};
210
211		conf {
212			groups = "sdio0_2_grp";
213			slew-rate = <0>;
214			io-standard = <1>;
215			bias-disable;
216		};
217
218		mux-cd {
219			groups = "gpio0_14_grp";
220			function = "sdio0_cd";
221		};
222
223		conf-cd {
224			groups = "gpio0_14_grp";
225			bias-high-impedance;
226			bias-pull-up;
227			slew-rate = <0>;
228			io-standard = <1>;
229		};
230
231		mux-wp {
232			groups = "gpio0_15_grp";
233			function = "sdio0_wp";
234		};
235
236		conf-wp {
237			groups = "gpio0_15_grp";
238			bias-high-impedance;
239			bias-pull-up;
240			slew-rate = <0>;
241			io-standard = <1>;
242		};
243	};
244
245	pinctrl_uart1_default: uart1-default {
246		mux {
247			groups = "uart1_10_grp";
248			function = "uart1";
249		};
250
251		conf {
252			groups = "uart1_10_grp";
253			slew-rate = <0>;
254			io-standard = <1>;
255		};
256
257		conf-rx {
258			pins = "MIO49";
259			bias-high-impedance;
260		};
261
262		conf-tx {
263			pins = "MIO48";
264			bias-disable;
265		};
266	};
267
268	pinctrl_usb0_default: usb0-default {
269		mux {
270			groups = "usb0_0_grp";
271			function = "usb0";
272		};
273
274		conf {
275			groups = "usb0_0_grp";
276			slew-rate = <0>;
277			io-standard = <1>;
278		};
279
280		conf-rx {
281			pins = "MIO29", "MIO31", "MIO36";
282			bias-high-impedance;
283		};
284
285		conf-tx {
286			pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
287			       "MIO35", "MIO37", "MIO38", "MIO39";
288			bias-disable;
289		};
290	};
291};
292
293&sdhci0 {
294	status = "okay";
295	pinctrl-names = "default";
296	pinctrl-0 = <&pinctrl_sdhci0_default>;
297};
298
299&uart1 {
300	u-boot,dm-pre-reloc;
301	status = "okay";
302	pinctrl-names = "default";
303	pinctrl-0 = <&pinctrl_uart1_default>;
304};
305
306&qspi {
307	status = "okay";
308};
309
310&usb0 {
311	status = "okay";
312	dr_mode = "host";
313	usb-phy = <&usb_phy0>;
314	pinctrl-names = "default";
315	pinctrl-0 = <&pinctrl_usb0_default>;
316};
317