1/* 2 * Xilinx ZC706 board DTS 3 * 4 * Copyright (C) 2011 - 2015 Xilinx 5 * Copyright (C) 2012 National Instruments Corp. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9/dts-v1/; 10#include "zynq-7000.dtsi" 11 12/ { 13 model = "Zynq ZC706 Development Board"; 14 compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000"; 15 16 aliases { 17 ethernet0 = &gem0; 18 i2c0 = &i2c0; 19 serial0 = &uart1; 20 spi0 = &qspi; 21 mmc0 = &sdhci0; 22 }; 23 24 memory@0 { 25 device_type = "memory"; 26 reg = <0x0 0x40000000>; 27 }; 28 29 chosen { 30 bootargs = ""; 31 stdout-path = "serial0:115200n8"; 32 }; 33 34 usb_phy0: phy0 { 35 compatible = "usb-nop-xceiv"; 36 #phy-cells = <0>; 37 }; 38}; 39 40&clkc { 41 ps-clk-frequency = <33333333>; 42}; 43 44&gem0 { 45 status = "okay"; 46 phy-mode = "rgmii-id"; 47 phy-handle = <ðernet_phy>; 48 pinctrl-names = "default"; 49 pinctrl-0 = <&pinctrl_gem0_default>; 50 51 ethernet_phy: ethernet-phy@7 { 52 reg = <7>; 53 }; 54}; 55 56&gpio0 { 57 pinctrl-names = "default"; 58 pinctrl-0 = <&pinctrl_gpio0_default>; 59}; 60 61&i2c0 { 62 status = "okay"; 63 clock-frequency = <400000>; 64 pinctrl-names = "default"; 65 pinctrl-0 = <&pinctrl_i2c0_default>; 66 67 i2cswitch@74 { 68 compatible = "nxp,pca9548"; 69 #address-cells = <1>; 70 #size-cells = <0>; 71 reg = <0x74>; 72 73 i2c@0 { 74 #address-cells = <1>; 75 #size-cells = <0>; 76 reg = <0>; 77 si570: clock-generator@5d { 78 #clock-cells = <0>; 79 compatible = "silabs,si570"; 80 temperature-stability = <50>; 81 reg = <0x5d>; 82 factory-fout = <156250000>; 83 clock-frequency = <148500000>; 84 }; 85 }; 86 87 i2c@1 { 88 #address-cells = <1>; 89 #size-cells = <0>; 90 reg = <1>; 91 adv7511: hdmi-tx@39 { 92 compatible = "adi,adv7511"; 93 reg = <0x39>; 94 adi,input-depth = <8>; 95 adi,input-colorspace = "yuv422"; 96 adi,input-clock = "1x"; 97 adi,input-style = <3>; 98 adi,input-justification = "evenly"; 99 }; 100 }; 101 102 i2c@2 { 103 #address-cells = <1>; 104 #size-cells = <0>; 105 reg = <2>; 106 eeprom@54 { 107 compatible = "at,24c08"; 108 reg = <0x54>; 109 }; 110 }; 111 112 i2c@3 { 113 #address-cells = <1>; 114 #size-cells = <0>; 115 reg = <3>; 116 gpio@21 { 117 compatible = "ti,tca6416"; 118 reg = <0x21>; 119 gpio-controller; 120 #gpio-cells = <2>; 121 }; 122 }; 123 124 i2c@4 { 125 #address-cells = <1>; 126 #size-cells = <0>; 127 reg = <4>; 128 rtc@51 { 129 compatible = "nxp,pcf8563"; 130 reg = <0x51>; 131 }; 132 }; 133 134 i2c@7 { 135 #address-cells = <1>; 136 #size-cells = <0>; 137 reg = <7>; 138 ucd90120@65 { 139 compatible = "ti,ucd90120"; 140 reg = <0x65>; 141 }; 142 }; 143 }; 144}; 145 146&pinctrl0 { 147 pinctrl_gem0_default: gem0-default { 148 mux { 149 function = "ethernet0"; 150 groups = "ethernet0_0_grp"; 151 }; 152 153 conf { 154 groups = "ethernet0_0_grp"; 155 slew-rate = <0>; 156 io-standard = <4>; 157 }; 158 159 conf-rx { 160 pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27"; 161 bias-high-impedance; 162 low-power-disable; 163 }; 164 165 conf-tx { 166 pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21"; 167 low-power-enable; 168 bias-disable; 169 }; 170 171 mux-mdio { 172 function = "mdio0"; 173 groups = "mdio0_0_grp"; 174 }; 175 176 conf-mdio { 177 groups = "mdio0_0_grp"; 178 slew-rate = <0>; 179 io-standard = <1>; 180 bias-disable; 181 }; 182 }; 183 184 pinctrl_gpio0_default: gpio0-default { 185 mux { 186 function = "gpio0"; 187 groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; 188 }; 189 190 conf { 191 groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp"; 192 slew-rate = <0>; 193 io-standard = <1>; 194 }; 195 196 conf-pull-up { 197 pins = "MIO46", "MIO47"; 198 bias-pull-up; 199 }; 200 201 conf-pull-none { 202 pins = "MIO7"; 203 bias-disable; 204 }; 205 }; 206 207 pinctrl_i2c0_default: i2c0-default { 208 mux { 209 groups = "i2c0_10_grp"; 210 function = "i2c0"; 211 }; 212 213 conf { 214 groups = "i2c0_10_grp"; 215 bias-pull-up; 216 slew-rate = <0>; 217 io-standard = <1>; 218 }; 219 }; 220 221 pinctrl_sdhci0_default: sdhci0-default { 222 mux { 223 groups = "sdio0_2_grp"; 224 function = "sdio0"; 225 }; 226 227 conf { 228 groups = "sdio0_2_grp"; 229 slew-rate = <0>; 230 io-standard = <1>; 231 bias-disable; 232 }; 233 234 mux-cd { 235 groups = "gpio0_14_grp"; 236 function = "sdio0_cd"; 237 }; 238 239 conf-cd { 240 groups = "gpio0_14_grp"; 241 bias-high-impedance; 242 bias-pull-up; 243 slew-rate = <0>; 244 io-standard = <1>; 245 }; 246 247 mux-wp { 248 groups = "gpio0_15_grp"; 249 function = "sdio0_wp"; 250 }; 251 252 conf-wp { 253 groups = "gpio0_15_grp"; 254 bias-high-impedance; 255 bias-pull-up; 256 slew-rate = <0>; 257 io-standard = <1>; 258 }; 259 }; 260 261 pinctrl_uart1_default: uart1-default { 262 mux { 263 groups = "uart1_10_grp"; 264 function = "uart1"; 265 }; 266 267 conf { 268 groups = "uart1_10_grp"; 269 slew-rate = <0>; 270 io-standard = <1>; 271 }; 272 273 conf-rx { 274 pins = "MIO49"; 275 bias-high-impedance; 276 }; 277 278 conf-tx { 279 pins = "MIO48"; 280 bias-disable; 281 }; 282 }; 283 284 pinctrl_usb0_default: usb0-default { 285 mux { 286 groups = "usb0_0_grp"; 287 function = "usb0"; 288 }; 289 290 conf { 291 groups = "usb0_0_grp"; 292 slew-rate = <0>; 293 io-standard = <1>; 294 }; 295 296 conf-rx { 297 pins = "MIO29", "MIO31", "MIO36"; 298 bias-high-impedance; 299 }; 300 301 conf-tx { 302 pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34", 303 "MIO35", "MIO37", "MIO38", "MIO39"; 304 bias-disable; 305 }; 306 }; 307}; 308 309&qspi { 310 u-boot,dm-pre-reloc; 311 status = "okay"; 312}; 313 314&sdhci0 { 315 u-boot,dm-pre-reloc; 316 status = "okay"; 317 pinctrl-names = "default"; 318 pinctrl-0 = <&pinctrl_sdhci0_default>; 319}; 320 321&uart1 { 322 u-boot,dm-pre-reloc; 323 status = "okay"; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&pinctrl_uart1_default>; 326}; 327 328&usb0 { 329 status = "okay"; 330 dr_mode = "host"; 331 usb-phy = <&usb_phy0>; 332 pinctrl-names = "default"; 333 pinctrl-0 = <&pinctrl_usb0_default>; 334}; 335