xref: /openbmc/u-boot/arch/arm/dts/zynq-zc702.dts (revision fdbb740d) 
1/*
2 * Xilinx ZC702 board DTS
3 *
4 *  Copyright (C) 2011 - 2015 Xilinx
5 *  Copyright (C) 2012 National Instruments Corp.
6 *
7 * SPDX-License-Identifier:	GPL-2.0+
8 */
9/dts-v1/;
10#include "zynq-7000.dtsi"
11
12/ {
13	model = "Zynq ZC702 Development Board";
14	compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
15
16	aliases {
17		ethernet0 = &gem0;
18		i2c0 = &i2c0;
19		serial0 = &uart1;
20		spi0 = &qspi;
21	};
22
23	memory {
24		device_type = "memory";
25		reg = <0x0 0x40000000>;
26	};
27
28	chosen {
29		bootargs = "earlyprintk";
30		stdout-path = "serial0:115200n8";
31	};
32
33	gpio-keys {
34		compatible = "gpio-keys";
35		#address-cells = <1>;
36		#size-cells = <0>;
37		autorepeat;
38		sw14 {
39			label = "sw14";
40			gpios = <&gpio0 12 0>;
41			linux,code = <108>; /* down */
42			gpio-key,wakeup;
43			autorepeat;
44		};
45		sw13 {
46			label = "sw13";
47			gpios = <&gpio0 14 0>;
48			linux,code = <103>; /* up */
49			gpio-key,wakeup;
50			autorepeat;
51		};
52	};
53
54	leds {
55		compatible = "gpio-leds";
56
57		ds23 {
58			label = "ds23";
59			gpios = <&gpio0 10 0>;
60			linux,default-trigger = "heartbeat";
61		};
62	};
63
64	usb_phy0: phy0 {
65		compatible = "usb-nop-xceiv";
66		#phy-cells = <0>;
67	};
68};
69
70&amba {
71	ocm: sram@fffc0000 {
72		compatible = "mmio-sram";
73		reg = <0xfffc0000 0x10000>;
74	};
75};
76
77&can0 {
78	status = "okay";
79	pinctrl-names = "default";
80	pinctrl-0 = <&pinctrl_can0_default>;
81};
82
83&clkc {
84	ps-clk-frequency = <33333333>;
85};
86
87&gem0 {
88	status = "okay";
89	phy-mode = "rgmii-id";
90	phy-handle = <&ethernet_phy>;
91	pinctrl-names = "default";
92	pinctrl-0 = <&pinctrl_gem0_default>;
93
94	ethernet_phy: ethernet-phy@7 {
95		reg = <7>;
96	};
97};
98
99&gpio0 {
100	pinctrl-names = "default";
101	pinctrl-0 = <&pinctrl_gpio0_default>;
102};
103
104&i2c0 {
105	status = "okay";
106	clock-frequency = <400000>;
107	pinctrl-names = "default";
108	pinctrl-0 = <&pinctrl_i2c0_default>;
109
110	i2cswitch@74 {
111		compatible = "nxp,pca9548";
112		#address-cells = <1>;
113		#size-cells = <0>;
114		reg = <0x74>;
115
116		i2c@0 {
117			#address-cells = <1>;
118			#size-cells = <0>;
119			reg = <0>;
120			si570: clock-generator@5d {
121				#clock-cells = <0>;
122				compatible = "silabs,si570";
123				temperature-stability = <50>;
124				reg = <0x5d>;
125				factory-fout = <156250000>;
126				clock-frequency = <148500000>;
127			};
128		};
129
130		i2c@2 {
131			#address-cells = <1>;
132			#size-cells = <0>;
133			reg = <2>;
134			eeprom@54 {
135				compatible = "at,24c08";
136				reg = <0x54>;
137			};
138		};
139
140		i2c@3 {
141			#address-cells = <1>;
142			#size-cells = <0>;
143			reg = <3>;
144			gpio@21 {
145				compatible = "ti,tca6416";
146				reg = <0x21>;
147				gpio-controller;
148				#gpio-cells = <2>;
149			};
150		};
151
152		i2c@4 {
153			#address-cells = <1>;
154			#size-cells = <0>;
155			reg = <4>;
156			rtc@51 {
157				compatible = "nxp,pcf8563";
158				reg = <0x51>;
159			};
160		};
161
162		i2c@7 {
163			#address-cells = <1>;
164			#size-cells = <0>;
165			reg = <7>;
166			hwmon@52 {
167				compatible = "ti,ucd9248";
168				reg = <52>;
169			};
170			hwmon@53 {
171				compatible = "ti,ucd9248";
172				reg = <53>;
173			};
174			hwmon@54 {
175				compatible = "ti,ucd9248";
176				reg = <54>;
177			};
178		};
179	};
180};
181
182&pinctrl0 {
183	pinctrl_can0_default: can0-default {
184		mux {
185			function = "can0";
186			groups = "can0_9_grp";
187		};
188
189		conf {
190			groups = "can0_9_grp";
191			slew-rate = <0>;
192			io-standard = <1>;
193		};
194
195		conf-rx {
196			pins = "MIO46";
197			bias-high-impedance;
198		};
199
200		conf-tx {
201			pins = "MIO47";
202			bias-disable;
203		};
204	};
205
206	pinctrl_gem0_default: gem0-default {
207		mux {
208			function = "ethernet0";
209			groups = "ethernet0_0_grp";
210		};
211
212		conf {
213			groups = "ethernet0_0_grp";
214			slew-rate = <0>;
215			io-standard = <4>;
216		};
217
218		conf-rx {
219			pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
220			bias-high-impedance;
221			low-power-disable;
222		};
223
224		conf-tx {
225			pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
226			bias-disable;
227			low-power-enable;
228		};
229
230		mux-mdio {
231			function = "mdio0";
232			groups = "mdio0_0_grp";
233		};
234
235		conf-mdio {
236			groups = "mdio0_0_grp";
237			slew-rate = <0>;
238			io-standard = <1>;
239			bias-disable;
240		};
241	};
242
243	pinctrl_gpio0_default: gpio0-default {
244		mux {
245			function = "gpio0";
246			groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
247				 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
248				 "gpio0_13_grp", "gpio0_14_grp";
249		};
250
251		conf {
252			groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
253				 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
254				 "gpio0_13_grp", "gpio0_14_grp";
255			slew-rate = <0>;
256			io-standard = <1>;
257		};
258
259		conf-pull-up {
260			pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
261			bias-pull-up;
262		};
263
264		conf-pull-none {
265			pins = "MIO7", "MIO8";
266			bias-disable;
267		};
268	};
269
270	pinctrl_i2c0_default: i2c0-default {
271		mux {
272			groups = "i2c0_10_grp";
273			function = "i2c0";
274		};
275
276		conf {
277			groups = "i2c0_10_grp";
278			bias-pull-up;
279			slew-rate = <0>;
280			io-standard = <1>;
281		};
282	};
283
284	pinctrl_sdhci0_default: sdhci0-default {
285		mux {
286			groups = "sdio0_2_grp";
287			function = "sdio0";
288		};
289
290		conf {
291			groups = "sdio0_2_grp";
292			slew-rate = <0>;
293			io-standard = <1>;
294			bias-disable;
295		};
296
297		mux-cd {
298			groups = "gpio0_0_grp";
299			function = "sdio0_cd";
300		};
301
302		conf-cd {
303			groups = "gpio0_0_grp";
304			bias-high-impedance;
305			bias-pull-up;
306			slew-rate = <0>;
307			io-standard = <1>;
308		};
309
310		mux-wp {
311			groups = "gpio0_15_grp";
312			function = "sdio0_wp";
313		};
314
315		conf-wp {
316			groups = "gpio0_15_grp";
317			bias-high-impedance;
318			bias-pull-up;
319			slew-rate = <0>;
320			io-standard = <1>;
321		};
322	};
323
324	pinctrl_uart1_default: uart1-default {
325		mux {
326			groups = "uart1_10_grp";
327			function = "uart1";
328		};
329
330		conf {
331			groups = "uart1_10_grp";
332			slew-rate = <0>;
333			io-standard = <1>;
334		};
335
336		conf-rx {
337			pins = "MIO49";
338			bias-high-impedance;
339		};
340
341		conf-tx {
342			pins = "MIO48";
343			bias-disable;
344		};
345	};
346
347	pinctrl_usb0_default: usb0-default {
348		mux {
349			groups = "usb0_0_grp";
350			function = "usb0";
351		};
352
353		conf {
354			groups = "usb0_0_grp";
355			slew-rate = <0>;
356			io-standard = <1>;
357		};
358
359		conf-rx {
360			pins = "MIO29", "MIO31", "MIO36";
361			bias-high-impedance;
362		};
363
364		conf-tx {
365			pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
366			       "MIO35", "MIO37", "MIO38", "MIO39";
367			bias-disable;
368		};
369	};
370};
371
372&sdhci0 {
373	status = "okay";
374	pinctrl-names = "default";
375	pinctrl-0 = <&pinctrl_sdhci0_default>;
376};
377
378&uart1 {
379	status = "okay";
380	pinctrl-names = "default";
381	pinctrl-0 = <&pinctrl_uart1_default>;
382};
383
384&qspi {
385	status = "okay";
386};
387
388&usb0 {
389	status = "okay";
390	dr_mode = "host";
391	usb-phy = <&usb_phy0>;
392	pinctrl-names = "default";
393	pinctrl-0 = <&pinctrl_usb0_default>;
394};
395