xref: /openbmc/u-boot/arch/arm/dts/zynq-zc702.dts (revision 103e83a1) 
1/*
2 * Xilinx ZC702 board DTS
3 *
4 *  Copyright (C) 2011 - 2015 Xilinx
5 *  Copyright (C) 2012 National Instruments Corp.
6 *
7 * SPDX-License-Identifier:	GPL-2.0+
8 */
9/dts-v1/;
10#include "zynq-7000.dtsi"
11
12/ {
13	model = "Zynq ZC702 Development Board";
14	compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
15
16	aliases {
17		ethernet0 = &gem0;
18		i2c0 = &i2c0;
19		serial0 = &uart1;
20		spi0 = &qspi;
21		mmc0 = &sdhci0;
22	};
23
24	memory@0 {
25		device_type = "memory";
26		reg = <0x0 0x40000000>;
27	};
28
29	chosen {
30		bootargs = "";
31		stdout-path = "serial0:115200n8";
32	};
33
34	gpio-keys {
35		compatible = "gpio-keys";
36		#address-cells = <1>;
37		#size-cells = <0>;
38		autorepeat;
39		sw14 {
40			label = "sw14";
41			gpios = <&gpio0 12 0>;
42			linux,code = <108>; /* down */
43			gpio-key,wakeup;
44			autorepeat;
45		};
46		sw13 {
47			label = "sw13";
48			gpios = <&gpio0 14 0>;
49			linux,code = <103>; /* up */
50			gpio-key,wakeup;
51			autorepeat;
52		};
53	};
54
55	leds {
56		compatible = "gpio-leds";
57
58		ds23 {
59			label = "ds23";
60			gpios = <&gpio0 10 0>;
61			linux,default-trigger = "heartbeat";
62		};
63	};
64
65	usb_phy0: phy0 {
66		compatible = "usb-nop-xceiv";
67		#phy-cells = <0>;
68	};
69};
70
71&amba {
72	ocm: sram@fffc0000 {
73		compatible = "mmio-sram";
74		reg = <0xfffc0000 0x10000>;
75	};
76};
77
78&can0 {
79	status = "okay";
80	pinctrl-names = "default";
81	pinctrl-0 = <&pinctrl_can0_default>;
82};
83
84&clkc {
85	ps-clk-frequency = <33333333>;
86};
87
88&gem0 {
89	status = "okay";
90	phy-mode = "rgmii-id";
91	phy-handle = <&ethernet_phy>;
92	pinctrl-names = "default";
93	pinctrl-0 = <&pinctrl_gem0_default>;
94	phy-reset-gpio = <&gpio0 11 0>;
95	phy-reset-active-low;
96
97	ethernet_phy: ethernet-phy@7 {
98		reg = <7>;
99	};
100};
101
102&gpio0 {
103	pinctrl-names = "default";
104	pinctrl-0 = <&pinctrl_gpio0_default>;
105};
106
107&i2c0 {
108	status = "okay";
109	clock-frequency = <400000>;
110	pinctrl-names = "default";
111	pinctrl-0 = <&pinctrl_i2c0_default>;
112
113	i2cswitch@74 {
114		compatible = "nxp,pca9548";
115		#address-cells = <1>;
116		#size-cells = <0>;
117		reg = <0x74>;
118
119		i2c@0 {
120			#address-cells = <1>;
121			#size-cells = <0>;
122			reg = <0>;
123			si570: clock-generator@5d {
124				#clock-cells = <0>;
125				compatible = "silabs,si570";
126				temperature-stability = <50>;
127				reg = <0x5d>;
128				factory-fout = <156250000>;
129				clock-frequency = <148500000>;
130			};
131		};
132
133		i2c@1 {
134			#address-cells = <1>;
135			#size-cells = <0>;
136			reg = <1>;
137			adv7511: hdmi-tx@39 {
138				compatible = "adi,adv7511";
139				reg = <0x39>;
140				adi,input-depth = <8>;
141				adi,input-colorspace = "yuv422";
142				adi,input-clock = "1x";
143				adi,input-style = <3>;
144				adi,input-justification = "right";
145			};
146		};
147
148		i2c@2 {
149			#address-cells = <1>;
150			#size-cells = <0>;
151			reg = <2>;
152			eeprom@54 {
153				compatible = "at,24c08";
154				reg = <0x54>;
155			};
156		};
157
158		i2c@3 {
159			#address-cells = <1>;
160			#size-cells = <0>;
161			reg = <3>;
162			gpio@21 {
163				compatible = "ti,tca6416";
164				reg = <0x21>;
165				gpio-controller;
166				#gpio-cells = <2>;
167			};
168		};
169
170		i2c@4 {
171			#address-cells = <1>;
172			#size-cells = <0>;
173			reg = <4>;
174			rtc@51 {
175				compatible = "nxp,pcf8563";
176				reg = <0x51>;
177			};
178		};
179
180		i2c@7 {
181			#address-cells = <1>;
182			#size-cells = <0>;
183			reg = <7>;
184			hwmon@52 {
185				compatible = "ti,ucd9248";
186				reg = <52>;
187			};
188			hwmon@53 {
189				compatible = "ti,ucd9248";
190				reg = <53>;
191			};
192			hwmon@54 {
193				compatible = "ti,ucd9248";
194				reg = <54>;
195			};
196		};
197	};
198};
199
200&pinctrl0 {
201	pinctrl_can0_default: can0-default {
202		mux {
203			function = "can0";
204			groups = "can0_9_grp";
205		};
206
207		conf {
208			groups = "can0_9_grp";
209			slew-rate = <0>;
210			io-standard = <1>;
211		};
212
213		conf-rx {
214			pins = "MIO46";
215			bias-high-impedance;
216		};
217
218		conf-tx {
219			pins = "MIO47";
220			bias-disable;
221		};
222	};
223
224	pinctrl_gem0_default: gem0-default {
225		mux {
226			function = "ethernet0";
227			groups = "ethernet0_0_grp";
228		};
229
230		conf {
231			groups = "ethernet0_0_grp";
232			slew-rate = <0>;
233			io-standard = <4>;
234		};
235
236		conf-rx {
237			pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
238			bias-high-impedance;
239			low-power-disable;
240		};
241
242		conf-tx {
243			pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
244			bias-disable;
245			low-power-enable;
246		};
247
248		mux-mdio {
249			function = "mdio0";
250			groups = "mdio0_0_grp";
251		};
252
253		conf-mdio {
254			groups = "mdio0_0_grp";
255			slew-rate = <0>;
256			io-standard = <1>;
257			bias-disable;
258		};
259	};
260
261	pinctrl_gpio0_default: gpio0-default {
262		mux {
263			function = "gpio0";
264			groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
265				 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
266				 "gpio0_13_grp", "gpio0_14_grp";
267		};
268
269		conf {
270			groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
271				 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
272				 "gpio0_13_grp", "gpio0_14_grp";
273			slew-rate = <0>;
274			io-standard = <1>;
275		};
276
277		conf-pull-up {
278			pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
279			bias-pull-up;
280		};
281
282		conf-pull-none {
283			pins = "MIO7", "MIO8";
284			bias-disable;
285		};
286	};
287
288	pinctrl_i2c0_default: i2c0-default {
289		mux {
290			groups = "i2c0_10_grp";
291			function = "i2c0";
292		};
293
294		conf {
295			groups = "i2c0_10_grp";
296			bias-pull-up;
297			slew-rate = <0>;
298			io-standard = <1>;
299		};
300	};
301
302	pinctrl_sdhci0_default: sdhci0-default {
303		mux {
304			groups = "sdio0_2_grp";
305			function = "sdio0";
306		};
307
308		conf {
309			groups = "sdio0_2_grp";
310			slew-rate = <0>;
311			io-standard = <1>;
312			bias-disable;
313		};
314
315		mux-cd {
316			groups = "gpio0_0_grp";
317			function = "sdio0_cd";
318		};
319
320		conf-cd {
321			groups = "gpio0_0_grp";
322			bias-high-impedance;
323			bias-pull-up;
324			slew-rate = <0>;
325			io-standard = <1>;
326		};
327
328		mux-wp {
329			groups = "gpio0_15_grp";
330			function = "sdio0_wp";
331		};
332
333		conf-wp {
334			groups = "gpio0_15_grp";
335			bias-high-impedance;
336			bias-pull-up;
337			slew-rate = <0>;
338			io-standard = <1>;
339		};
340	};
341
342	pinctrl_uart1_default: uart1-default {
343		mux {
344			groups = "uart1_10_grp";
345			function = "uart1";
346		};
347
348		conf {
349			groups = "uart1_10_grp";
350			slew-rate = <0>;
351			io-standard = <1>;
352		};
353
354		conf-rx {
355			pins = "MIO49";
356			bias-high-impedance;
357		};
358
359		conf-tx {
360			pins = "MIO48";
361			bias-disable;
362		};
363	};
364
365	pinctrl_usb0_default: usb0-default {
366		mux {
367			groups = "usb0_0_grp";
368			function = "usb0";
369		};
370
371		conf {
372			groups = "usb0_0_grp";
373			slew-rate = <0>;
374			io-standard = <1>;
375		};
376
377		conf-rx {
378			pins = "MIO29", "MIO31", "MIO36";
379			bias-high-impedance;
380		};
381
382		conf-tx {
383			pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
384			       "MIO35", "MIO37", "MIO38", "MIO39";
385			bias-disable;
386		};
387	};
388};
389
390&qspi {
391	u-boot,dm-pre-reloc;
392	status = "okay";
393};
394
395&sdhci0 {
396	u-boot,dm-pre-reloc;
397	status = "okay";
398	pinctrl-names = "default";
399	pinctrl-0 = <&pinctrl_sdhci0_default>;
400};
401
402&uart1 {
403	u-boot,dm-pre-reloc;
404	status = "okay";
405	pinctrl-names = "default";
406	pinctrl-0 = <&pinctrl_uart1_default>;
407};
408
409&usb0 {
410	status = "okay";
411	dr_mode = "host";
412	usb-phy = <&usb_phy0>;
413	pinctrl-names = "default";
414	pinctrl-0 = <&pinctrl_usb0_default>;
415};
416