1/* 2 * Xilinx CSE QSPI board DTS 3 * 4 * Copyright (C) 2015 - 2017 Xilinx, Inc. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8/dts-v1/; 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 model = "Zynq CSE QSPI Board"; 14 compatible = "xlnx,zynq-cse-qspi", "xlnx,zynq-7000"; 15 16 aliases { 17 spi0 = &qspi; 18 serial0 = &dcc; 19 }; 20 21 memory@fffc0000 { 22 device_type = "memory"; 23 reg = <0xFFFC0000 0x40000>; 24 }; 25 26 chosen { 27 stdout-path = "serial0:115200n8"; 28 }; 29 30 dcc: dcc { 31 compatible = "arm,dcc"; 32 status = "disabled"; 33 u-boot,dm-pre-reloc; 34 }; 35 36 amba: amba { 37 u-boot,dm-pre-reloc; 38 compatible = "simple-bus"; 39 #address-cells = <1>; 40 #size-cells = <1>; 41 interrupt-parent = <&intc>; 42 ranges; 43 44 intc: interrupt-controller@f8f01000 { 45 compatible = "arm,cortex-a9-gic"; 46 #interrupt-cells = <3>; 47 interrupt-controller; 48 reg = <0xF8F01000 0x1000>, 49 <0xF8F00100 0x100>; 50 }; 51 52 qspi: spi@e000d000 { 53 clock-names = "ref_clk", "pclk"; 54 clocks = <&clkc 10>, <&clkc 43>; 55 compatible = "xlnx,zynq-qspi-1.0"; 56 status = "okay"; 57 interrupt-parent = <&intc>; 58 interrupts = <0 19 4>; 59 reg = <0xe000d000 0x1000>; 60 #address-cells = <1>; 61 #size-cells = <0>; 62 num-cs = <1>; 63 flash@0 { 64 compatible = "n25q128a11"; 65 reg = <0x0>; 66 spi-tx-bus-width = <1>; 67 spi-rx-bus-width = <4>; 68 spi-max-frequency = <50000000>; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 partition@qspi-fsbl-uboot { 72 label = "qspi-fsbl-uboot"; 73 reg = <0x0 0x100000>; 74 }; 75 partition@qspi-linux { 76 label = "qspi-linux"; 77 reg = <0x100000 0x500000>; 78 }; 79 partition@qspi-device-tree { 80 label = "qspi-device-tree"; 81 reg = <0x600000 0x20000>; 82 }; 83 partition@qspi-rootfs { 84 label = "qspi-rootfs"; 85 reg = <0x620000 0x5E0000>; 86 }; 87 partition@qspi-bitstream { 88 label = "qspi-bitstream"; 89 reg = <0xC00000 0x400000>; 90 }; 91 }; 92 }; 93 94 slcr: slcr@f8000000 { 95 u-boot,dm-pre-reloc; 96 #address-cells = <1>; 97 #size-cells = <1>; 98 compatible = "xlnx,zynq-slcr", "syscon", "simple-bus"; 99 reg = <0xF8000000 0x1000>; 100 ranges; 101 clkc: clkc@100 { 102 #clock-cells = <1>; 103 compatible = "xlnx,ps7-clkc"; 104 fclk-enable = <0xf>; 105 u-boot,dm-pre-reloc; 106 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", 107 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", 108 "dci", "lqspi", "smc", "pcap", "gem0", "gem1", 109 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", 110 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", 111 "dma", "usb0_aper", "usb1_aper", "gem0_aper", 112 "gem1_aper", "sdio0_aper", "sdio1_aper", 113 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", 114 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", 115 "gpio_aper", "lqspi_aper", "smc_aper", "swdt", 116 "dbg_trc", "dbg_apb"; 117 reg = <0x100 0x100>; 118 }; 119 }; 120 }; 121 122}; 123 124&dcc { 125 status = "okay"; 126}; 127