1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Xilinx CSE NOR board DTS 4 * 5 * Copyright (C) 2018 Xilinx, Inc. 6 */ 7/dts-v1/; 8#include "zynq-7000.dtsi" 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 model = "Zynq CSE NOR Board"; 14 compatible = "xlnx,zynq-cse-nor", "xlnx,zynq-7000"; 15 16 aliases { 17 serial0 = &dcc; 18 }; 19 20 memory@fffc0000 { 21 device_type = "memory"; 22 reg = <0xFFFC0000 0x40000>; 23 }; 24 25 chosen { 26 stdout-path = "serial0:115200n8"; 27 }; 28 29 dcc: dcc { 30 compatible = "arm,dcc"; 31 status = "disabled"; 32 u-boot,dm-pre-reloc; 33 }; 34 35 amba: amba { 36 compatible = "simple-bus"; 37 #address-cells = <1>; 38 #size-cells = <1>; 39 interrupt-parent = <&intc>; 40 ranges; 41 42 intc: interrupt-controller@f8f01000 { 43 compatible = "arm,cortex-a9-gic"; 44 #interrupt-cells = <3>; 45 interrupt-controller; 46 reg = <0xF8F01000 0x1000>, 47 <0xF8F00100 0x100>; 48 }; 49 50 slcr: slcr@f8000000 { 51 #address-cells = <1>; 52 #size-cells = <1>; 53 compatible = "xlnx,zynq-slcr", "syscon", "simple-bus"; 54 reg = <0xF8000000 0x1000>; 55 ranges; 56 clkc: clkc@100 { 57 #clock-cells = <1>; 58 compatible = "xlnx,ps7-clkc"; 59 clock-output-names = "armpll", "ddrpll", 60 "iopll", "cpu_6or4x", 61 "cpu_3or2x", "cpu_2x", "cpu_1x", 62 "ddr2x", "ddr3x", "dci", 63 "lqspi", "smc", "pcap", "gem0", 64 "gem1", "fclk0", "fclk1", 65 "fclk2", "fclk3", "can0", 66 "can1", "sdio0", "sdio1", 67 "uart0", "uart1", "spi0", 68 "spi1", "dma", "usb0_aper", 69 "usb1_aper", "gem0_aper", 70 "gem1_aper", "sdio0_aper", 71 "sdio1_aper", "spi0_aper", 72 "spi1_aper", "can0_aper", 73 "can1_aper", "i2c0_aper", 74 "i2c1_aper", "uart0_aper", 75 "uart1_aper", "gpio_aper", 76 "lqspi_aper", "smc_aper", 77 "swdt", "dbg_trc", "dbg_apb"; 78 reg = <0x100 0x100>; 79 }; 80 }; 81 }; 82}; 83 84&dcc { 85 status = "okay"; 86}; 87