xref: /openbmc/u-boot/arch/arm/dts/zynq-7000.dtsi (revision c00d0012)
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Xilinx Zynq 7000 DTSI
4 * Describes the hardware common to all Zynq 7000-based boards.
5 *
6 *  Copyright (C) 2011 - 2015 Xilinx
7 */
8
9/ {
10	#address-cells = <1>;
11	#size-cells = <1>;
12	compatible = "xlnx,zynq-7000";
13
14	cpus {
15		#address-cells = <1>;
16		#size-cells = <0>;
17
18		cpu0: cpu@0 {
19			compatible = "arm,cortex-a9";
20			device_type = "cpu";
21			reg = <0>;
22			clocks = <&clkc 3>;
23			clock-latency = <1000>;
24			cpu0-supply = <&regulator_vccpint>;
25			operating-points = <
26				/* kHz    uV */
27				666667  1000000
28				333334  1000000
29			>;
30		};
31
32		cpu1: cpu@1 {
33			compatible = "arm,cortex-a9";
34			device_type = "cpu";
35			reg = <1>;
36			clocks = <&clkc 3>;
37		};
38	};
39
40	fpga_full: fpga-full {
41		compatible = "fpga-region";
42		fpga-mgr = <&devcfg>;
43		#address-cells = <1>;
44		#size-cells = <1>;
45		ranges;
46	};
47
48	pmu@f8891000 {
49		compatible = "arm,cortex-a9-pmu";
50		interrupts = <0 5 4>, <0 6 4>;
51		interrupt-parent = <&intc>;
52		reg = <0xf8891000 0x1000>,
53		      <0xf8893000 0x1000>;
54	};
55
56	regulator_vccpint: fixedregulator {
57		compatible = "regulator-fixed";
58		regulator-name = "VCCPINT";
59		regulator-min-microvolt = <1000000>;
60		regulator-max-microvolt = <1000000>;
61		regulator-boot-on;
62		regulator-always-on;
63	};
64
65	amba: amba {
66		u-boot,dm-pre-reloc;
67		compatible = "simple-bus";
68		#address-cells = <1>;
69		#size-cells = <1>;
70		interrupt-parent = <&intc>;
71		ranges;
72
73		adc: adc@f8007100 {
74			compatible = "xlnx,zynq-xadc-1.00.a";
75			reg = <0xf8007100 0x20>;
76			interrupts = <0 7 4>;
77			interrupt-parent = <&intc>;
78			clocks = <&clkc 12>;
79		};
80
81		can0: can@e0008000 {
82			compatible = "xlnx,zynq-can-1.0";
83			status = "disabled";
84			clocks = <&clkc 19>, <&clkc 36>;
85			clock-names = "can_clk", "pclk";
86			reg = <0xe0008000 0x1000>;
87			interrupts = <0 28 4>;
88			interrupt-parent = <&intc>;
89			tx-fifo-depth = <0x40>;
90			rx-fifo-depth = <0x40>;
91		};
92
93		can1: can@e0009000 {
94			compatible = "xlnx,zynq-can-1.0";
95			status = "disabled";
96			clocks = <&clkc 20>, <&clkc 37>;
97			clock-names = "can_clk", "pclk";
98			reg = <0xe0009000 0x1000>;
99			interrupts = <0 51 4>;
100			interrupt-parent = <&intc>;
101			tx-fifo-depth = <0x40>;
102			rx-fifo-depth = <0x40>;
103		};
104
105		gpio0: gpio@e000a000 {
106			compatible = "xlnx,zynq-gpio-1.0";
107			#gpio-cells = <2>;
108			clocks = <&clkc 42>;
109			gpio-controller;
110			interrupt-controller;
111			#interrupt-cells = <2>;
112			interrupt-parent = <&intc>;
113			interrupts = <0 20 4>;
114			reg = <0xe000a000 0x1000>;
115		};
116
117		i2c0: i2c@e0004000 {
118			compatible = "cdns,i2c-r1p10";
119			status = "disabled";
120			clocks = <&clkc 38>;
121			interrupt-parent = <&intc>;
122			interrupts = <0 25 4>;
123			reg = <0xe0004000 0x1000>;
124			#address-cells = <1>;
125			#size-cells = <0>;
126		};
127
128		i2c1: i2c@e0005000 {
129			compatible = "cdns,i2c-r1p10";
130			status = "disabled";
131			clocks = <&clkc 39>;
132			interrupt-parent = <&intc>;
133			interrupts = <0 48 4>;
134			reg = <0xe0005000 0x1000>;
135			#address-cells = <1>;
136			#size-cells = <0>;
137		};
138
139		intc: interrupt-controller@f8f01000 {
140			compatible = "arm,cortex-a9-gic";
141			#interrupt-cells = <3>;
142			interrupt-controller;
143			reg = <0xF8F01000 0x1000>,
144			      <0xF8F00100 0x100>;
145		};
146
147		L2: cache-controller@f8f02000 {
148			compatible = "arm,pl310-cache";
149			reg = <0xF8F02000 0x1000>;
150			interrupts = <0 2 4>;
151			arm,data-latency = <3 2 2>;
152			arm,tag-latency = <2 2 2>;
153			cache-unified;
154			cache-level = <2>;
155		};
156
157		mc: memory-controller@f8006000 {
158			compatible = "xlnx,zynq-ddrc-a05";
159			reg = <0xf8006000 0x1000>;
160		};
161
162		uart0: serial@e0000000 {
163			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
164			status = "disabled";
165			clocks = <&clkc 23>, <&clkc 40>;
166			clock-names = "uart_clk", "pclk";
167			reg = <0xE0000000 0x1000>;
168			interrupts = <0 27 4>;
169		};
170
171		uart1: serial@e0001000 {
172			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
173			status = "disabled";
174			clocks = <&clkc 24>, <&clkc 41>;
175			clock-names = "uart_clk", "pclk";
176			reg = <0xE0001000 0x1000>;
177			interrupts = <0 50 4>;
178		};
179
180		spi0: spi@e0006000 {
181			compatible = "xlnx,zynq-spi-r1p6";
182			reg = <0xe0006000 0x1000>;
183			status = "disabled";
184			interrupt-parent = <&intc>;
185			interrupts = <0 26 4>;
186			clocks = <&clkc 25>, <&clkc 34>;
187			clock-names = "ref_clk", "pclk";
188			#address-cells = <1>;
189			#size-cells = <0>;
190		};
191
192		spi1: spi@e0007000 {
193			compatible = "xlnx,zynq-spi-r1p6";
194			reg = <0xe0007000 0x1000>;
195			status = "disabled";
196			interrupt-parent = <&intc>;
197			interrupts = <0 49 4>;
198			clocks = <&clkc 26>, <&clkc 35>;
199			clock-names = "ref_clk", "pclk";
200			#address-cells = <1>;
201			#size-cells = <0>;
202		};
203
204		qspi: spi@e000d000 {
205			clock-names = "ref_clk", "pclk";
206			clocks = <&clkc 10>, <&clkc 43>;
207			compatible = "xlnx,zynq-qspi-1.0";
208			status = "disabled";
209			interrupt-parent = <&intc>;
210			interrupts = <0 19 4>;
211			reg = <0xe000d000 0x1000>;
212			#address-cells = <1>;
213			#size-cells = <0>;
214		};
215
216		gem0: ethernet@e000b000 {
217			compatible = "cdns,zynq-gem", "cdns,gem";
218			reg = <0xe000b000 0x1000>;
219			status = "disabled";
220			interrupts = <0 22 4>;
221			clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
222			clock-names = "pclk", "hclk", "tx_clk";
223			#address-cells = <1>;
224			#size-cells = <0>;
225		};
226
227		gem1: ethernet@e000c000 {
228			compatible = "cdns,zynq-gem", "cdns,gem";
229			reg = <0xe000c000 0x1000>;
230			status = "disabled";
231			interrupts = <0 45 4>;
232			clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
233			clock-names = "pclk", "hclk", "tx_clk";
234			#address-cells = <1>;
235			#size-cells = <0>;
236		};
237
238		sdhci0: sdhci@e0100000 {
239			compatible = "arasan,sdhci-8.9a";
240			status = "disabled";
241			clock-names = "clk_xin", "clk_ahb";
242			clocks = <&clkc 21>, <&clkc 32>;
243			interrupt-parent = <&intc>;
244			interrupts = <0 24 4>;
245			reg = <0xe0100000 0x1000>;
246		};
247
248		sdhci1: sdhci@e0101000 {
249			compatible = "arasan,sdhci-8.9a";
250			status = "disabled";
251			clock-names = "clk_xin", "clk_ahb";
252			clocks = <&clkc 22>, <&clkc 33>;
253			interrupt-parent = <&intc>;
254			interrupts = <0 47 4>;
255			reg = <0xe0101000 0x1000>;
256		};
257
258		slcr: slcr@f8000000 {
259			u-boot,dm-pre-reloc;
260			#address-cells = <1>;
261			#size-cells = <1>;
262			compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
263			reg = <0xF8000000 0x1000>;
264			ranges;
265			clkc: clkc@100 {
266				u-boot,dm-pre-reloc;
267				#clock-cells = <1>;
268				compatible = "xlnx,ps7-clkc";
269				fclk-enable = <0>;
270				clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
271						"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
272						"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
273						"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
274						"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
275						"dma", "usb0_aper", "usb1_aper", "gem0_aper",
276						"gem1_aper", "sdio0_aper", "sdio1_aper",
277						"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
278						"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
279						"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
280						"dbg_trc", "dbg_apb";
281				reg = <0x100 0x100>;
282			};
283
284			rstc: rstc@200 {
285				compatible = "xlnx,zynq-reset";
286				reg = <0x200 0x48>;
287				#reset-cells = <1>;
288				syscon = <&slcr>;
289			};
290
291			pinctrl0: pinctrl@700 {
292				compatible = "xlnx,pinctrl-zynq";
293				reg = <0x700 0x200>;
294				syscon = <&slcr>;
295			};
296		};
297
298		dmac_s: dmac@f8003000 {
299			compatible = "arm,pl330", "arm,primecell";
300			reg = <0xf8003000 0x1000>;
301			interrupt-parent = <&intc>;
302			interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
303				"dma4", "dma5", "dma6", "dma7";
304			interrupts = <0 13 4>,
305			             <0 14 4>, <0 15 4>,
306			             <0 16 4>, <0 17 4>,
307			             <0 40 4>, <0 41 4>,
308			             <0 42 4>, <0 43 4>;
309			#dma-cells = <1>;
310			#dma-channels = <8>;
311			#dma-requests = <4>;
312			clocks = <&clkc 27>;
313			clock-names = "apb_pclk";
314		};
315
316		devcfg: devcfg@f8007000 {
317			compatible = "xlnx,zynq-devcfg-1.0";
318			interrupt-parent = <&intc>;
319			interrupts = <0 8 4>;
320			reg = <0xf8007000 0x100>;
321			clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
322			clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
323			syscon = <&slcr>;
324		};
325
326		efuse: efuse@f800d000 {
327			compatible = "xlnx,zynq-efuse";
328			reg = <0xf800d000 0x20>;
329		};
330
331		global_timer: timer@f8f00200 {
332			compatible = "arm,cortex-a9-global-timer";
333			reg = <0xf8f00200 0x20>;
334			interrupts = <1 11 0x301>;
335			interrupt-parent = <&intc>;
336			clocks = <&clkc 4>;
337		};
338
339		ttc0: timer@f8001000 {
340			interrupt-parent = <&intc>;
341			interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
342			compatible = "cdns,ttc";
343			clocks = <&clkc 6>;
344			reg = <0xF8001000 0x1000>;
345		};
346
347		ttc1: timer@f8002000 {
348			interrupt-parent = <&intc>;
349			interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
350			compatible = "cdns,ttc";
351			clocks = <&clkc 6>;
352			reg = <0xF8002000 0x1000>;
353		};
354
355		scutimer: timer@f8f00600 {
356			interrupt-parent = <&intc>;
357			interrupts = <1 13 0x301>;
358			compatible = "arm,cortex-a9-twd-timer";
359			reg = <0xf8f00600 0x20>;
360			clocks = <&clkc 4>;
361		};
362
363		usb0: usb@e0002000 {
364			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
365			status = "disabled";
366			clocks = <&clkc 28>;
367			interrupt-parent = <&intc>;
368			interrupts = <0 21 4>;
369			reg = <0xe0002000 0x1000>;
370			phy_type = "ulpi";
371		};
372
373		usb1: usb@e0003000 {
374			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
375			status = "disabled";
376			clocks = <&clkc 29>;
377			interrupt-parent = <&intc>;
378			interrupts = <0 44 4>;
379			reg = <0xe0003000 0x1000>;
380			phy_type = "ulpi";
381		};
382
383		watchdog0: watchdog@f8005000 {
384			clocks = <&clkc 45>;
385			compatible = "cdns,wdt-r1p2";
386			interrupt-parent = <&intc>;
387			interrupts = <0 9 1>;
388			reg = <0xf8005000 0x1000>;
389			timeout-sec = <10>;
390		};
391	};
392};
393