1/* 2 * Xilinx Zynq 7000 DTSI 3 * Describes the hardware common to all Zynq 7000-based boards. 4 * 5 * Copyright (C) 2011 - 2015 Xilinx 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 compatible = "xlnx,zynq-7000"; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 compatible = "arm,cortex-a9"; 21 device_type = "cpu"; 22 reg = <0>; 23 clocks = <&clkc 3>; 24 clock-latency = <1000>; 25 cpu0-supply = <®ulator_vccpint>; 26 operating-points = < 27 /* kHz uV */ 28 666667 1000000 29 333334 1000000 30 >; 31 }; 32 33 cpu1: cpu@1 { 34 compatible = "arm,cortex-a9"; 35 device_type = "cpu"; 36 reg = <1>; 37 clocks = <&clkc 3>; 38 }; 39 }; 40 41 fpga_full: fpga-full { 42 compatible = "fpga-region"; 43 fpga-mgr = <&devcfg>; 44 #address-cells = <1>; 45 #size-cells = <1>; 46 ranges; 47 }; 48 49 pmu@f8891000 { 50 compatible = "arm,cortex-a9-pmu"; 51 interrupts = <0 5 4>, <0 6 4>; 52 interrupt-parent = <&intc>; 53 reg = <0xf8891000 0x1000>, 54 <0xf8893000 0x1000>; 55 }; 56 57 regulator_vccpint: fixedregulator { 58 compatible = "regulator-fixed"; 59 regulator-name = "VCCPINT"; 60 regulator-min-microvolt = <1000000>; 61 regulator-max-microvolt = <1000000>; 62 regulator-boot-on; 63 regulator-always-on; 64 }; 65 66 amba: amba { 67 u-boot,dm-pre-reloc; 68 compatible = "simple-bus"; 69 #address-cells = <1>; 70 #size-cells = <1>; 71 interrupt-parent = <&intc>; 72 ranges; 73 74 adc: adc@f8007100 { 75 compatible = "xlnx,zynq-xadc-1.00.a"; 76 reg = <0xf8007100 0x20>; 77 interrupts = <0 7 4>; 78 interrupt-parent = <&intc>; 79 clocks = <&clkc 12>; 80 }; 81 82 can0: can@e0008000 { 83 compatible = "xlnx,zynq-can-1.0"; 84 status = "disabled"; 85 clocks = <&clkc 19>, <&clkc 36>; 86 clock-names = "can_clk", "pclk"; 87 reg = <0xe0008000 0x1000>; 88 interrupts = <0 28 4>; 89 interrupt-parent = <&intc>; 90 tx-fifo-depth = <0x40>; 91 rx-fifo-depth = <0x40>; 92 }; 93 94 can1: can@e0009000 { 95 compatible = "xlnx,zynq-can-1.0"; 96 status = "disabled"; 97 clocks = <&clkc 20>, <&clkc 37>; 98 clock-names = "can_clk", "pclk"; 99 reg = <0xe0009000 0x1000>; 100 interrupts = <0 51 4>; 101 interrupt-parent = <&intc>; 102 tx-fifo-depth = <0x40>; 103 rx-fifo-depth = <0x40>; 104 }; 105 106 gpio0: gpio@e000a000 { 107 compatible = "xlnx,zynq-gpio-1.0"; 108 #gpio-cells = <2>; 109 clocks = <&clkc 42>; 110 gpio-controller; 111 interrupt-controller; 112 #interrupt-cells = <2>; 113 interrupt-parent = <&intc>; 114 interrupts = <0 20 4>; 115 reg = <0xe000a000 0x1000>; 116 }; 117 118 i2c0: i2c@e0004000 { 119 compatible = "cdns,i2c-r1p10"; 120 status = "disabled"; 121 clocks = <&clkc 38>; 122 interrupt-parent = <&intc>; 123 interrupts = <0 25 4>; 124 reg = <0xe0004000 0x1000>; 125 #address-cells = <1>; 126 #size-cells = <0>; 127 }; 128 129 i2c1: i2c@e0005000 { 130 compatible = "cdns,i2c-r1p10"; 131 status = "disabled"; 132 clocks = <&clkc 39>; 133 interrupt-parent = <&intc>; 134 interrupts = <0 48 4>; 135 reg = <0xe0005000 0x1000>; 136 #address-cells = <1>; 137 #size-cells = <0>; 138 }; 139 140 intc: interrupt-controller@f8f01000 { 141 compatible = "arm,cortex-a9-gic"; 142 #interrupt-cells = <3>; 143 interrupt-controller; 144 reg = <0xF8F01000 0x1000>, 145 <0xF8F00100 0x100>; 146 }; 147 148 L2: cache-controller@f8f02000 { 149 compatible = "arm,pl310-cache"; 150 reg = <0xF8F02000 0x1000>; 151 interrupts = <0 2 4>; 152 arm,data-latency = <3 2 2>; 153 arm,tag-latency = <2 2 2>; 154 cache-unified; 155 cache-level = <2>; 156 }; 157 158 mc: memory-controller@f8006000 { 159 compatible = "xlnx,zynq-ddrc-a05"; 160 reg = <0xf8006000 0x1000>; 161 }; 162 163 uart0: serial@e0000000 { 164 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 165 status = "disabled"; 166 clocks = <&clkc 23>, <&clkc 40>; 167 clock-names = "uart_clk", "pclk"; 168 reg = <0xE0000000 0x1000>; 169 interrupts = <0 27 4>; 170 }; 171 172 uart1: serial@e0001000 { 173 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 174 status = "disabled"; 175 clocks = <&clkc 24>, <&clkc 41>; 176 clock-names = "uart_clk", "pclk"; 177 reg = <0xE0001000 0x1000>; 178 interrupts = <0 50 4>; 179 }; 180 181 spi0: spi@e0006000 { 182 compatible = "xlnx,zynq-spi-r1p6"; 183 reg = <0xe0006000 0x1000>; 184 status = "disabled"; 185 interrupt-parent = <&intc>; 186 interrupts = <0 26 4>; 187 clocks = <&clkc 25>, <&clkc 34>; 188 clock-names = "ref_clk", "pclk"; 189 #address-cells = <1>; 190 #size-cells = <0>; 191 }; 192 193 spi1: spi@e0007000 { 194 compatible = "xlnx,zynq-spi-r1p6"; 195 reg = <0xe0007000 0x1000>; 196 status = "disabled"; 197 interrupt-parent = <&intc>; 198 interrupts = <0 49 4>; 199 clocks = <&clkc 26>, <&clkc 35>; 200 clock-names = "ref_clk", "pclk"; 201 #address-cells = <1>; 202 #size-cells = <0>; 203 }; 204 205 qspi: spi@e000d000 { 206 clock-names = "ref_clk", "pclk"; 207 clocks = <&clkc 10>, <&clkc 43>; 208 compatible = "xlnx,zynq-qspi-1.0"; 209 status = "disabled"; 210 interrupt-parent = <&intc>; 211 interrupts = <0 19 4>; 212 reg = <0xe000d000 0x1000>; 213 #address-cells = <1>; 214 #size-cells = <0>; 215 }; 216 217 gem0: ethernet@e000b000 { 218 compatible = "cdns,zynq-gem", "cdns,gem"; 219 reg = <0xe000b000 0x1000>; 220 status = "disabled"; 221 interrupts = <0 22 4>; 222 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 223 clock-names = "pclk", "hclk", "tx_clk"; 224 #address-cells = <1>; 225 #size-cells = <0>; 226 }; 227 228 gem1: ethernet@e000c000 { 229 compatible = "cdns,zynq-gem", "cdns,gem"; 230 reg = <0xe000c000 0x1000>; 231 status = "disabled"; 232 interrupts = <0 45 4>; 233 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; 234 clock-names = "pclk", "hclk", "tx_clk"; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 }; 238 239 sdhci0: sdhci@e0100000 { 240 compatible = "arasan,sdhci-8.9a"; 241 status = "disabled"; 242 clock-names = "clk_xin", "clk_ahb"; 243 clocks = <&clkc 21>, <&clkc 32>; 244 interrupt-parent = <&intc>; 245 interrupts = <0 24 4>; 246 reg = <0xe0100000 0x1000>; 247 }; 248 249 sdhci1: sdhci@e0101000 { 250 compatible = "arasan,sdhci-8.9a"; 251 status = "disabled"; 252 clock-names = "clk_xin", "clk_ahb"; 253 clocks = <&clkc 22>, <&clkc 33>; 254 interrupt-parent = <&intc>; 255 interrupts = <0 47 4>; 256 reg = <0xe0101000 0x1000>; 257 }; 258 259 slcr: slcr@f8000000 { 260 u-boot,dm-pre-reloc; 261 #address-cells = <1>; 262 #size-cells = <1>; 263 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; 264 reg = <0xF8000000 0x1000>; 265 ranges; 266 clkc: clkc@100 { 267 u-boot,dm-pre-reloc; 268 #clock-cells = <1>; 269 compatible = "xlnx,ps7-clkc"; 270 fclk-enable = <0>; 271 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", 272 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", 273 "dci", "lqspi", "smc", "pcap", "gem0", "gem1", 274 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", 275 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", 276 "dma", "usb0_aper", "usb1_aper", "gem0_aper", 277 "gem1_aper", "sdio0_aper", "sdio1_aper", 278 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", 279 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", 280 "gpio_aper", "lqspi_aper", "smc_aper", "swdt", 281 "dbg_trc", "dbg_apb"; 282 reg = <0x100 0x100>; 283 }; 284 285 rstc: rstc@200 { 286 compatible = "xlnx,zynq-reset"; 287 reg = <0x200 0x48>; 288 #reset-cells = <1>; 289 syscon = <&slcr>; 290 }; 291 292 pinctrl0: pinctrl@700 { 293 compatible = "xlnx,pinctrl-zynq"; 294 reg = <0x700 0x200>; 295 syscon = <&slcr>; 296 }; 297 }; 298 299 dmac_s: dmac@f8003000 { 300 compatible = "arm,pl330", "arm,primecell"; 301 reg = <0xf8003000 0x1000>; 302 interrupt-parent = <&intc>; 303 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", 304 "dma4", "dma5", "dma6", "dma7"; 305 interrupts = <0 13 4>, 306 <0 14 4>, <0 15 4>, 307 <0 16 4>, <0 17 4>, 308 <0 40 4>, <0 41 4>, 309 <0 42 4>, <0 43 4>; 310 #dma-cells = <1>; 311 #dma-channels = <8>; 312 #dma-requests = <4>; 313 clocks = <&clkc 27>; 314 clock-names = "apb_pclk"; 315 }; 316 317 devcfg: devcfg@f8007000 { 318 compatible = "xlnx,zynq-devcfg-1.0"; 319 interrupt-parent = <&intc>; 320 interrupts = <0 8 4>; 321 reg = <0xf8007000 0x100>; 322 clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; 323 clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; 324 syscon = <&slcr>; 325 }; 326 327 global_timer: timer@f8f00200 { 328 compatible = "arm,cortex-a9-global-timer"; 329 reg = <0xf8f00200 0x20>; 330 interrupts = <1 11 0x301>; 331 interrupt-parent = <&intc>; 332 clocks = <&clkc 4>; 333 }; 334 335 ttc0: timer@f8001000 { 336 interrupt-parent = <&intc>; 337 interrupts = <0 10 4>, <0 11 4>, <0 12 4>; 338 compatible = "cdns,ttc"; 339 clocks = <&clkc 6>; 340 reg = <0xF8001000 0x1000>; 341 }; 342 343 ttc1: timer@f8002000 { 344 interrupt-parent = <&intc>; 345 interrupts = <0 37 4>, <0 38 4>, <0 39 4>; 346 compatible = "cdns,ttc"; 347 clocks = <&clkc 6>; 348 reg = <0xF8002000 0x1000>; 349 }; 350 351 scutimer: timer@f8f00600 { 352 interrupt-parent = <&intc>; 353 interrupts = <1 13 0x301>; 354 compatible = "arm,cortex-a9-twd-timer"; 355 reg = <0xf8f00600 0x20>; 356 clocks = <&clkc 4>; 357 }; 358 359 usb0: usb@e0002000 { 360 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 361 status = "disabled"; 362 clocks = <&clkc 28>; 363 interrupt-parent = <&intc>; 364 interrupts = <0 21 4>; 365 reg = <0xe0002000 0x1000>; 366 phy_type = "ulpi"; 367 }; 368 369 usb1: usb@e0003000 { 370 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 371 status = "disabled"; 372 clocks = <&clkc 29>; 373 interrupt-parent = <&intc>; 374 interrupts = <0 44 4>; 375 reg = <0xe0003000 0x1000>; 376 phy_type = "ulpi"; 377 }; 378 379 watchdog0: watchdog@f8005000 { 380 clocks = <&clkc 45>; 381 compatible = "cdns,wdt-r1p2"; 382 interrupt-parent = <&intc>; 383 interrupts = <0 9 1>; 384 reg = <0xf8005000 0x1000>; 385 timeout-sec = <10>; 386 }; 387 }; 388}; 389