1/* 2 * Xilinx Zynq 7000 DTSI 3 * Describes the hardware common to all Zynq 7000-based boards. 4 * 5 * Copyright (C) 2011 - 2015 Xilinx 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 compatible = "xlnx,zynq-7000"; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu@0 { 20 compatible = "arm,cortex-a9"; 21 device_type = "cpu"; 22 reg = <0>; 23 clocks = <&clkc 3>; 24 clock-latency = <1000>; 25 cpu0-supply = <®ulator_vccpint>; 26 operating-points = < 27 /* kHz uV */ 28 666667 1000000 29 333334 1000000 30 >; 31 }; 32 33 cpu@1 { 34 compatible = "arm,cortex-a9"; 35 device_type = "cpu"; 36 reg = <1>; 37 clocks = <&clkc 3>; 38 }; 39 }; 40 41 pmu@f8891000 { 42 compatible = "arm,cortex-a9-pmu"; 43 interrupts = <0 5 4>, <0 6 4>; 44 interrupt-parent = <&intc>; 45 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; 46 }; 47 48 regulator_vccpint: fixedregulator { 49 compatible = "regulator-fixed"; 50 regulator-name = "VCCPINT"; 51 regulator-min-microvolt = <1000000>; 52 regulator-max-microvolt = <1000000>; 53 regulator-boot-on; 54 regulator-always-on; 55 }; 56 57 amba: amba { 58 u-boot,dm-pre-reloc; 59 compatible = "simple-bus"; 60 #address-cells = <1>; 61 #size-cells = <1>; 62 interrupt-parent = <&intc>; 63 ranges; 64 65 adc: adc@f8007100 { 66 compatible = "xlnx,zynq-xadc-1.00.a"; 67 reg = <0xf8007100 0x20>; 68 interrupts = <0 7 4>; 69 interrupt-parent = <&intc>; 70 clocks = <&clkc 12>; 71 }; 72 73 can0: can@e0008000 { 74 compatible = "xlnx,zynq-can-1.0"; 75 status = "disabled"; 76 clocks = <&clkc 19>, <&clkc 36>; 77 clock-names = "can_clk", "pclk"; 78 reg = <0xe0008000 0x1000>; 79 interrupts = <0 28 4>; 80 interrupt-parent = <&intc>; 81 tx-fifo-depth = <0x40>; 82 rx-fifo-depth = <0x40>; 83 }; 84 85 can1: can@e0009000 { 86 compatible = "xlnx,zynq-can-1.0"; 87 status = "disabled"; 88 clocks = <&clkc 20>, <&clkc 37>; 89 clock-names = "can_clk", "pclk"; 90 reg = <0xe0009000 0x1000>; 91 interrupts = <0 51 4>; 92 interrupt-parent = <&intc>; 93 tx-fifo-depth = <0x40>; 94 rx-fifo-depth = <0x40>; 95 }; 96 97 gpio0: gpio@e000a000 { 98 compatible = "xlnx,zynq-gpio-1.0"; 99 #gpio-cells = <2>; 100 #interrupt-cells = <2>; 101 clocks = <&clkc 42>; 102 gpio-controller; 103 interrupt-controller; 104 interrupt-parent = <&intc>; 105 interrupts = <0 20 4>; 106 reg = <0xe000a000 0x1000>; 107 }; 108 109 i2c0: i2c@e0004000 { 110 compatible = "cdns,i2c-r1p10"; 111 status = "disabled"; 112 clocks = <&clkc 38>; 113 interrupt-parent = <&intc>; 114 interrupts = <0 25 4>; 115 reg = <0xe0004000 0x1000>; 116 #address-cells = <1>; 117 #size-cells = <0>; 118 }; 119 120 i2c1: i2c@e0005000 { 121 compatible = "cdns,i2c-r1p10"; 122 status = "disabled"; 123 clocks = <&clkc 39>; 124 interrupt-parent = <&intc>; 125 interrupts = <0 48 4>; 126 reg = <0xe0005000 0x1000>; 127 #address-cells = <1>; 128 #size-cells = <0>; 129 }; 130 131 intc: interrupt-controller@f8f01000 { 132 compatible = "arm,cortex-a9-gic"; 133 #interrupt-cells = <3>; 134 interrupt-controller; 135 reg = <0xF8F01000 0x1000>, 136 <0xF8F00100 0x100>; 137 }; 138 139 L2: cache-controller@f8f02000 { 140 compatible = "arm,pl310-cache"; 141 reg = <0xF8F02000 0x1000>; 142 interrupts = <0 2 4>; 143 arm,data-latency = <3 2 2>; 144 arm,tag-latency = <2 2 2>; 145 cache-unified; 146 cache-level = <2>; 147 }; 148 149 mc: memory-controller@f8006000 { 150 compatible = "xlnx,zynq-ddrc-a05"; 151 reg = <0xf8006000 0x1000>; 152 }; 153 154 uart0: serial@e0000000 { 155 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 156 status = "disabled"; 157 clocks = <&clkc 23>, <&clkc 40>; 158 clock-names = "uart_clk", "pclk"; 159 reg = <0xE0000000 0x1000>; 160 interrupts = <0 27 4>; 161 }; 162 163 uart1: serial@e0001000 { 164 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 165 status = "disabled"; 166 clocks = <&clkc 24>, <&clkc 41>; 167 clock-names = "uart_clk", "pclk"; 168 reg = <0xE0001000 0x1000>; 169 interrupts = <0 50 4>; 170 }; 171 172 spi0: spi@e0006000 { 173 compatible = "xlnx,zynq-spi-r1p6"; 174 reg = <0xe0006000 0x1000>; 175 status = "disabled"; 176 interrupt-parent = <&intc>; 177 interrupts = <0 26 4>; 178 clocks = <&clkc 25>, <&clkc 34>; 179 clock-names = "ref_clk", "pclk"; 180 spi-max-frequency = <166666700>; 181 #address-cells = <1>; 182 #size-cells = <0>; 183 }; 184 185 spi1: spi@e0007000 { 186 compatible = "xlnx,zynq-spi-r1p6"; 187 reg = <0xe0007000 0x1000>; 188 status = "disabled"; 189 interrupt-parent = <&intc>; 190 interrupts = <0 49 4>; 191 clocks = <&clkc 26>, <&clkc 35>; 192 clock-names = "ref_clk", "pclk"; 193 spi-max-frequency = <166666700>; 194 #address-cells = <1>; 195 #size-cells = <0>; 196 }; 197 198 qspi: spi@e000d000 { 199 clock-names = "ref_clk", "pclk"; 200 clocks = <&clkc 10>, <&clkc 43>; 201 compatible = "xlnx,zynq-qspi-1.0"; 202 status = "disabled"; 203 interrupt-parent = <&intc>; 204 interrupts = <0 19 4>; 205 reg = <0xe000d000 0x1000>; 206 #address-cells = <1>; 207 #size-cells = <0>; 208 }; 209 210 gem0: ethernet@e000b000 { 211 compatible = "cdns,zynq-gem", "cdns,gem"; 212 reg = <0xe000b000 0x1000>; 213 status = "disabled"; 214 interrupts = <0 22 4>; 215 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 216 clock-names = "pclk", "hclk", "tx_clk"; 217 #address-cells = <1>; 218 #size-cells = <0>; 219 }; 220 221 gem1: ethernet@e000c000 { 222 compatible = "cdns,zynq-gem", "cdns,gem"; 223 reg = <0xe000c000 0x1000>; 224 status = "disabled"; 225 interrupts = <0 45 4>; 226 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; 227 clock-names = "pclk", "hclk", "tx_clk"; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 }; 231 232 sdhci0: sdhci@e0100000 { 233 compatible = "arasan,sdhci-8.9a"; 234 status = "disabled"; 235 clock-names = "clk_xin", "clk_ahb"; 236 clocks = <&clkc 21>, <&clkc 32>; 237 interrupt-parent = <&intc>; 238 interrupts = <0 24 4>; 239 reg = <0xe0100000 0x1000>; 240 }; 241 242 sdhci1: sdhci@e0101000 { 243 compatible = "arasan,sdhci-8.9a"; 244 status = "disabled"; 245 clock-names = "clk_xin", "clk_ahb"; 246 clocks = <&clkc 22>, <&clkc 33>; 247 interrupt-parent = <&intc>; 248 interrupts = <0 47 4>; 249 reg = <0xe0101000 0x1000>; 250 }; 251 252 slcr: slcr@f8000000 { 253 #address-cells = <1>; 254 #size-cells = <1>; 255 compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd"; 256 reg = <0xF8000000 0x1000>; 257 ranges; 258 clkc: clkc@100 { 259 #clock-cells = <1>; 260 compatible = "xlnx,ps7-clkc"; 261 fclk-enable = <0>; 262 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", 263 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", 264 "dci", "lqspi", "smc", "pcap", "gem0", "gem1", 265 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", 266 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", 267 "dma", "usb0_aper", "usb1_aper", "gem0_aper", 268 "gem1_aper", "sdio0_aper", "sdio1_aper", 269 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", 270 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", 271 "gpio_aper", "lqspi_aper", "smc_aper", "swdt", 272 "dbg_trc", "dbg_apb"; 273 reg = <0x100 0x100>; 274 }; 275 276 rstc: rstc@200 { 277 compatible = "xlnx,zynq-reset"; 278 reg = <0x200 0x48>; 279 #reset-cells = <1>; 280 syscon = <&slcr>; 281 }; 282 283 pinctrl0: pinctrl@700 { 284 compatible = "xlnx,pinctrl-zynq"; 285 reg = <0x700 0x200>; 286 syscon = <&slcr>; 287 }; 288 }; 289 290 dmac_s: dmac@f8003000 { 291 compatible = "arm,pl330", "arm,primecell"; 292 reg = <0xf8003000 0x1000>; 293 interrupt-parent = <&intc>; 294 interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", 295 "dma4", "dma5", "dma6", "dma7"; 296 interrupts = <0 13 4>, 297 <0 14 4>, <0 15 4>, 298 <0 16 4>, <0 17 4>, 299 <0 40 4>, <0 41 4>, 300 <0 42 4>, <0 43 4>; 301 #dma-cells = <1>; 302 #dma-channels = <8>; 303 #dma-requests = <4>; 304 clocks = <&clkc 27>; 305 clock-names = "apb_pclk"; 306 }; 307 308 devcfg: devcfg@f8007000 { 309 compatible = "xlnx,zynq-devcfg-1.0"; 310 interrupt-parent = <&intc>; 311 interrupts = <0 8 4>; 312 reg = <0xf8007000 0x100>; 313 clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; 314 clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; 315 syscon = <&slcr>; 316 }; 317 318 global_timer: timer@f8f00200 { 319 compatible = "arm,cortex-a9-global-timer"; 320 reg = <0xf8f00200 0x20>; 321 interrupts = <1 11 0x301>; 322 interrupt-parent = <&intc>; 323 clocks = <&clkc 4>; 324 }; 325 326 ttc0: timer@f8001000 { 327 interrupt-parent = <&intc>; 328 interrupts = <0 10 4>, <0 11 4>, <0 12 4>; 329 compatible = "cdns,ttc"; 330 clocks = <&clkc 6>; 331 reg = <0xF8001000 0x1000>; 332 }; 333 334 ttc1: timer@f8002000 { 335 interrupt-parent = <&intc>; 336 interrupts = <0 37 4>, <0 38 4>, <0 39 4>; 337 compatible = "cdns,ttc"; 338 clocks = <&clkc 6>; 339 reg = <0xF8002000 0x1000>; 340 }; 341 342 scutimer: timer@f8f00600 { 343 interrupt-parent = <&intc>; 344 interrupts = <1 13 0x301>; 345 compatible = "arm,cortex-a9-twd-timer"; 346 reg = <0xf8f00600 0x20>; 347 clocks = <&clkc 4>; 348 }; 349 350 usb0: usb@e0002000 { 351 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 352 status = "disabled"; 353 clocks = <&clkc 28>; 354 interrupt-parent = <&intc>; 355 interrupts = <0 21 4>; 356 reg = <0xe0002000 0x1000>; 357 phy_type = "ulpi"; 358 }; 359 360 usb1: usb@e0003000 { 361 compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2"; 362 status = "disabled"; 363 clocks = <&clkc 29>; 364 interrupt-parent = <&intc>; 365 interrupts = <0 44 4>; 366 reg = <0xe0003000 0x1000>; 367 phy_type = "ulpi"; 368 }; 369 370 watchdog0: watchdog@f8005000 { 371 clocks = <&clkc 45>; 372 compatible = "cdns,wdt-r1p2"; 373 interrupt-parent = <&intc>; 374 interrupts = <0 9 1>; 375 reg = <0xf8005000 0x1000>; 376 timeout-sec = <10>; 377 }; 378 }; 379}; 380