1/* 2 * Xilinx Zynq 7000 DTSI 3 * Describes the hardware common to all Zynq 7000-based boards. 4 * 5 * Copyright (C) 2013 Xilinx, Inc. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9/include/ "skeleton.dtsi" 10 11/ { 12 compatible = "xlnx,zynq-7000"; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu@0 { 19 compatible = "arm,cortex-a9"; 20 device_type = "cpu"; 21 reg = <0>; 22 clocks = <&clkc 3>; 23 clock-latency = <1000>; 24 operating-points = < 25 /* kHz uV */ 26 666667 1000000 27 333334 1000000 28 222223 1000000 29 >; 30 }; 31 32 cpu@1 { 33 compatible = "arm,cortex-a9"; 34 device_type = "cpu"; 35 reg = <1>; 36 clocks = <&clkc 3>; 37 }; 38 }; 39 40 pmu { 41 compatible = "arm,cortex-a9-pmu"; 42 interrupts = <0 5 4>, <0 6 4>; 43 interrupt-parent = <&intc>; 44 reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; 45 }; 46 47 amba { 48 compatible = "simple-bus"; 49 #address-cells = <1>; 50 #size-cells = <1>; 51 interrupt-parent = <&intc>; 52 ranges; 53 54 i2c0: zynq-i2c@e0004000 { 55 compatible = "cdns,i2c-r1p10"; 56 status = "disabled"; 57 clocks = <&clkc 38>; 58 interrupt-parent = <&intc>; 59 interrupts = <0 25 4>; 60 reg = <0xe0004000 0x1000>; 61 #address-cells = <1>; 62 #size-cells = <0>; 63 }; 64 65 i2c1: zynq-i2c@e0005000 { 66 compatible = "cdns,i2c-r1p10"; 67 status = "disabled"; 68 clocks = <&clkc 39>; 69 interrupt-parent = <&intc>; 70 interrupts = <0 48 4>; 71 reg = <0xe0005000 0x1000>; 72 #address-cells = <1>; 73 #size-cells = <0>; 74 }; 75 76 intc: interrupt-controller@f8f01000 { 77 compatible = "arm,cortex-a9-gic"; 78 #interrupt-cells = <3>; 79 #address-cells = <1>; 80 interrupt-controller; 81 reg = <0xF8F01000 0x1000>, 82 <0xF8F00100 0x100>; 83 }; 84 85 L2: cache-controller { 86 compatible = "arm,pl310-cache"; 87 reg = <0xF8F02000 0x1000>; 88 arm,data-latency = <3 2 2>; 89 arm,tag-latency = <2 2 2>; 90 cache-unified; 91 cache-level = <2>; 92 }; 93 94 uart0: uart@e0000000 { 95 compatible = "xlnx,xuartps"; 96 status = "disabled"; 97 clocks = <&clkc 23>, <&clkc 40>; 98 clock-names = "ref_clk", "aper_clk"; 99 reg = <0xE0000000 0x1000>; 100 interrupts = <0 27 4>; 101 }; 102 103 uart1: uart@e0001000 { 104 compatible = "xlnx,xuartps"; 105 status = "disabled"; 106 clocks = <&clkc 24>, <&clkc 41>; 107 clock-names = "ref_clk", "aper_clk"; 108 reg = <0xE0001000 0x1000>; 109 interrupts = <0 50 4>; 110 }; 111 112 spi0: spi@e0006000 { 113 compatible = "xlnx,zynq-spi"; 114 reg = <0xe0006000 0x1000>; 115 status = "disabled"; 116 interrupt-parent = <&intc>; 117 interrupts = <0 26 4>; 118 clocks = <&clkc 25>, <&clkc 34>; 119 clock-names = "ref_clk", "pclk"; 120 spi-max-frequency = <166666700>; 121 #address-cells = <1>; 122 #size-cells = <0>; 123 }; 124 125 spi1: spi@e0007000 { 126 compatible = "xlnx,zynq-spi"; 127 reg = <0xe0007000 0x1000>; 128 status = "disabled"; 129 interrupt-parent = <&intc>; 130 interrupts = <0 49 4>; 131 clocks = <&clkc 26>, <&clkc 35>; 132 clock-names = "ref_clk", "pclk"; 133 spi-max-frequency = <166666700>; 134 #address-cells = <1>; 135 #size-cells = <0>; 136 }; 137 138 gem0: ethernet@e000b000 { 139 compatible = "cdns,gem"; 140 reg = <0xe000b000 0x4000>; 141 status = "disabled"; 142 interrupts = <0 22 4>; 143 clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; 144 clock-names = "pclk", "hclk", "tx_clk"; 145 }; 146 147 gem1: ethernet@e000c000 { 148 compatible = "cdns,gem"; 149 reg = <0xe000c000 0x4000>; 150 status = "disabled"; 151 interrupts = <0 45 4>; 152 clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; 153 clock-names = "pclk", "hclk", "tx_clk"; 154 }; 155 156 sdhci0: ps7-sdhci@e0100000 { 157 compatible = "arasan,sdhci-8.9a"; 158 status = "disabled"; 159 clock-names = "clk_xin", "clk_ahb"; 160 clocks = <&clkc 21>, <&clkc 32>; 161 interrupt-parent = <&intc>; 162 interrupts = <0 24 4>; 163 reg = <0xe0100000 0x1000>; 164 } ; 165 166 sdhci1: ps7-sdhci@e0101000 { 167 compatible = "arasan,sdhci-8.9a"; 168 status = "disabled"; 169 clock-names = "clk_xin", "clk_ahb"; 170 clocks = <&clkc 22>, <&clkc 33>; 171 interrupt-parent = <&intc>; 172 interrupts = <0 47 4>; 173 reg = <0xe0101000 0x1000>; 174 } ; 175 176 slcr: slcr@f8000000 { 177 #address-cells = <1>; 178 #size-cells = <1>; 179 compatible = "xlnx,zynq-slcr", "syscon"; 180 reg = <0xF8000000 0x1000>; 181 ranges; 182 clkc: clkc@100 { 183 #clock-cells = <1>; 184 compatible = "xlnx,ps7-clkc"; 185 ps-clk-frequency = <33333333>; 186 fclk-enable = <0>; 187 clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", 188 "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", 189 "dci", "lqspi", "smc", "pcap", "gem0", "gem1", 190 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", 191 "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", 192 "dma", "usb0_aper", "usb1_aper", "gem0_aper", 193 "gem1_aper", "sdio0_aper", "sdio1_aper", 194 "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", 195 "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", 196 "gpio_aper", "lqspi_aper", "smc_aper", "swdt", 197 "dbg_trc", "dbg_apb"; 198 reg = <0x100 0x100>; 199 }; 200 }; 201 202 global_timer: timer@f8f00200 { 203 compatible = "arm,cortex-a9-global-timer"; 204 reg = <0xf8f00200 0x20>; 205 interrupts = <1 11 0x301>; 206 interrupt-parent = <&intc>; 207 clocks = <&clkc 4>; 208 }; 209 210 ttc0: ttc0@f8001000 { 211 interrupt-parent = <&intc>; 212 interrupts = < 0 10 4 0 11 4 0 12 4 >; 213 compatible = "cdns,ttc"; 214 clocks = <&clkc 6>; 215 reg = <0xF8001000 0x1000>; 216 }; 217 218 ttc1: ttc1@f8002000 { 219 interrupt-parent = <&intc>; 220 interrupts = < 0 37 4 0 38 4 0 39 4 >; 221 compatible = "cdns,ttc"; 222 clocks = <&clkc 6>; 223 reg = <0xF8002000 0x1000>; 224 }; 225 scutimer: scutimer@f8f00600 { 226 interrupt-parent = <&intc>; 227 interrupts = < 1 13 0x301 >; 228 compatible = "arm,cortex-a9-twd-timer"; 229 reg = < 0xf8f00600 0x20 >; 230 clocks = <&clkc 4>; 231 } ; 232 }; 233}; 234