1/* 2 * Device Tree Source for UniPhier sLD8 SoC 3 * 4 * Copyright (C) 2015-2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 */ 9 10/ { 11 compatible = "socionext,uniphier-sld8"; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu@0 { 20 device_type = "cpu"; 21 compatible = "arm,cortex-a9"; 22 reg = <0>; 23 enable-method = "psci"; 24 next-level-cache = <&l2>; 25 }; 26 }; 27 28 psci { 29 compatible = "arm,psci-0.2"; 30 method = "smc"; 31 }; 32 33 clocks { 34 refclk: ref { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <25000000>; 38 }; 39 40 arm_timer_clk: arm_timer_clk { 41 #clock-cells = <0>; 42 compatible = "fixed-clock"; 43 clock-frequency = <50000000>; 44 }; 45 }; 46 47 soc { 48 compatible = "simple-bus"; 49 #address-cells = <1>; 50 #size-cells = <1>; 51 ranges; 52 interrupt-parent = <&intc>; 53 54 l2: l2-cache@500c0000 { 55 compatible = "socionext,uniphier-system-cache"; 56 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, 57 <0x506c0000 0x400>; 58 interrupts = <0 174 4>, <0 175 4>; 59 cache-unified; 60 cache-size = <(256 * 1024)>; 61 cache-sets = <256>; 62 cache-line-size = <128>; 63 cache-level = <2>; 64 }; 65 66 serial0: serial@54006800 { 67 compatible = "socionext,uniphier-uart"; 68 status = "disabled"; 69 reg = <0x54006800 0x40>; 70 interrupts = <0 33 4>; 71 pinctrl-names = "default"; 72 pinctrl-0 = <&pinctrl_uart0>; 73 clocks = <&peri_clk 0>; 74 clock-frequency = <80000000>; 75 }; 76 77 serial1: serial@54006900 { 78 compatible = "socionext,uniphier-uart"; 79 status = "disabled"; 80 reg = <0x54006900 0x40>; 81 interrupts = <0 35 4>; 82 pinctrl-names = "default"; 83 pinctrl-0 = <&pinctrl_uart1>; 84 clocks = <&peri_clk 1>; 85 clock-frequency = <80000000>; 86 }; 87 88 serial2: serial@54006a00 { 89 compatible = "socionext,uniphier-uart"; 90 status = "disabled"; 91 reg = <0x54006a00 0x40>; 92 interrupts = <0 37 4>; 93 pinctrl-names = "default"; 94 pinctrl-0 = <&pinctrl_uart2>; 95 clocks = <&peri_clk 2>; 96 clock-frequency = <80000000>; 97 }; 98 99 serial3: serial@54006b00 { 100 compatible = "socionext,uniphier-uart"; 101 status = "disabled"; 102 reg = <0x54006b00 0x40>; 103 interrupts = <0 29 4>; 104 pinctrl-names = "default"; 105 pinctrl-0 = <&pinctrl_uart3>; 106 clocks = <&peri_clk 3>; 107 clock-frequency = <80000000>; 108 }; 109 110 gpio: gpio@55000000 { 111 compatible = "socionext,uniphier-gpio"; 112 reg = <0x55000000 0x200>; 113 interrupt-parent = <&aidet>; 114 interrupt-controller; 115 #interrupt-cells = <2>; 116 gpio-controller; 117 #gpio-cells = <2>; 118 gpio-ranges = <&pinctrl 0 0 0>, 119 <&pinctrl 104 0 0>, 120 <&pinctrl 112 0 0>; 121 gpio-ranges-group-names = "gpio_range0", 122 "gpio_range1", 123 "gpio_range2"; 124 ngpios = <136>; 125 }; 126 127 i2c0: i2c@58400000 { 128 compatible = "socionext,uniphier-i2c"; 129 status = "disabled"; 130 reg = <0x58400000 0x40>; 131 #address-cells = <1>; 132 #size-cells = <0>; 133 interrupts = <0 41 1>; 134 pinctrl-names = "default"; 135 pinctrl-0 = <&pinctrl_i2c0>; 136 clocks = <&peri_clk 4>; 137 clock-frequency = <100000>; 138 }; 139 140 i2c1: i2c@58480000 { 141 compatible = "socionext,uniphier-i2c"; 142 status = "disabled"; 143 reg = <0x58480000 0x40>; 144 #address-cells = <1>; 145 #size-cells = <0>; 146 interrupts = <0 42 1>; 147 pinctrl-names = "default"; 148 pinctrl-0 = <&pinctrl_i2c1>; 149 clocks = <&peri_clk 5>; 150 clock-frequency = <100000>; 151 }; 152 153 /* chip-internal connection for DMD */ 154 i2c2: i2c@58500000 { 155 compatible = "socionext,uniphier-i2c"; 156 reg = <0x58500000 0x40>; 157 #address-cells = <1>; 158 #size-cells = <0>; 159 interrupts = <0 43 1>; 160 pinctrl-names = "default"; 161 pinctrl-0 = <&pinctrl_i2c2>; 162 clocks = <&peri_clk 6>; 163 clock-frequency = <400000>; 164 }; 165 166 i2c3: i2c@58580000 { 167 compatible = "socionext,uniphier-i2c"; 168 status = "disabled"; 169 reg = <0x58580000 0x40>; 170 #address-cells = <1>; 171 #size-cells = <0>; 172 interrupts = <0 44 1>; 173 pinctrl-names = "default"; 174 pinctrl-0 = <&pinctrl_i2c3>; 175 clocks = <&peri_clk 7>; 176 clock-frequency = <100000>; 177 }; 178 179 system_bus: system-bus@58c00000 { 180 compatible = "socionext,uniphier-system-bus"; 181 status = "disabled"; 182 reg = <0x58c00000 0x400>; 183 #address-cells = <2>; 184 #size-cells = <1>; 185 pinctrl-names = "default"; 186 pinctrl-0 = <&pinctrl_system_bus>; 187 }; 188 189 smpctrl@59801000 { 190 compatible = "socionext,uniphier-smpctrl"; 191 reg = <0x59801000 0x400>; 192 }; 193 194 mioctrl@59810000 { 195 compatible = "socionext,uniphier-sld8-mioctrl", 196 "simple-mfd", "syscon"; 197 reg = <0x59810000 0x800>; 198 199 mio_clk: clock { 200 compatible = "socionext,uniphier-sld8-mio-clock"; 201 #clock-cells = <1>; 202 }; 203 204 mio_rst: reset { 205 compatible = "socionext,uniphier-sld8-mio-reset"; 206 #reset-cells = <1>; 207 }; 208 }; 209 210 perictrl@59820000 { 211 compatible = "socionext,uniphier-sld8-perictrl", 212 "simple-mfd", "syscon"; 213 reg = <0x59820000 0x200>; 214 215 peri_clk: clock { 216 compatible = "socionext,uniphier-sld8-peri-clock"; 217 #clock-cells = <1>; 218 }; 219 220 peri_rst: reset { 221 compatible = "socionext,uniphier-sld8-peri-reset"; 222 #reset-cells = <1>; 223 }; 224 }; 225 226 sd: sdhc@5a400000 { 227 compatible = "socionext,uniphier-sdhc"; 228 status = "disabled"; 229 reg = <0x5a400000 0x200>; 230 interrupts = <0 76 4>; 231 pinctrl-names = "default", "1.8v"; 232 pinctrl-0 = <&pinctrl_sd>; 233 pinctrl-1 = <&pinctrl_sd_1v8>; 234 clocks = <&mio_clk 0>; 235 reset-names = "host", "bridge"; 236 resets = <&mio_rst 0>, <&mio_rst 3>; 237 bus-width = <4>; 238 cap-sd-highspeed; 239 sd-uhs-sdr12; 240 sd-uhs-sdr25; 241 sd-uhs-sdr50; 242 }; 243 244 emmc: sdhc@5a500000 { 245 compatible = "socionext,uniphier-sdhc"; 246 status = "disabled"; 247 reg = <0x5a500000 0x200>; 248 interrupts = <0 78 4>; 249 pinctrl-names = "default", "1.8v"; 250 pinctrl-0 = <&pinctrl_emmc>; 251 pinctrl-1 = <&pinctrl_emmc_1v8>; 252 clocks = <&mio_clk 1>; 253 reset-names = "host", "bridge"; 254 resets = <&mio_rst 1>, <&mio_rst 4>; 255 bus-width = <8>; 256 non-removable; 257 cap-mmc-highspeed; 258 cap-mmc-hw-reset; 259 }; 260 261 usb0: usb@5a800100 { 262 compatible = "socionext,uniphier-ehci", "generic-ehci"; 263 status = "disabled"; 264 reg = <0x5a800100 0x100>; 265 interrupts = <0 80 4>; 266 pinctrl-names = "default"; 267 pinctrl-0 = <&pinctrl_usb0>; 268 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; 269 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 270 <&mio_rst 12>; 271 }; 272 273 usb1: usb@5a810100 { 274 compatible = "socionext,uniphier-ehci", "generic-ehci"; 275 status = "disabled"; 276 reg = <0x5a810100 0x100>; 277 interrupts = <0 81 4>; 278 pinctrl-names = "default"; 279 pinctrl-0 = <&pinctrl_usb1>; 280 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; 281 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 282 <&mio_rst 13>; 283 }; 284 285 usb2: usb@5a820100 { 286 compatible = "socionext,uniphier-ehci", "generic-ehci"; 287 status = "disabled"; 288 reg = <0x5a820100 0x100>; 289 interrupts = <0 82 4>; 290 pinctrl-names = "default"; 291 pinctrl-0 = <&pinctrl_usb2>; 292 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; 293 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, 294 <&mio_rst 14>; 295 }; 296 297 soc-glue@5f800000 { 298 compatible = "socionext,uniphier-sld8-soc-glue", 299 "simple-mfd", "syscon"; 300 reg = <0x5f800000 0x2000>; 301 302 pinctrl: pinctrl { 303 compatible = "socionext,uniphier-sld8-pinctrl"; 304 }; 305 }; 306 307 timer@60000200 { 308 compatible = "arm,cortex-a9-global-timer"; 309 reg = <0x60000200 0x20>; 310 interrupts = <1 11 0x104>; 311 clocks = <&arm_timer_clk>; 312 }; 313 314 timer@60000600 { 315 compatible = "arm,cortex-a9-twd-timer"; 316 reg = <0x60000600 0x20>; 317 interrupts = <1 13 0x104>; 318 clocks = <&arm_timer_clk>; 319 }; 320 321 intc: interrupt-controller@60001000 { 322 compatible = "arm,cortex-a9-gic"; 323 reg = <0x60001000 0x1000>, 324 <0x60000100 0x100>; 325 #interrupt-cells = <3>; 326 interrupt-controller; 327 }; 328 329 aidet: aidet@61830000 { 330 compatible = "socionext,uniphier-sld8-aidet"; 331 reg = <0x61830000 0x200>; 332 interrupt-controller; 333 #interrupt-cells = <2>; 334 }; 335 336 sysctrl@61840000 { 337 compatible = "socionext,uniphier-sld8-sysctrl", 338 "simple-mfd", "syscon"; 339 reg = <0x61840000 0x10000>; 340 341 sys_clk: clock { 342 compatible = "socionext,uniphier-sld8-clock"; 343 #clock-cells = <1>; 344 }; 345 346 sys_rst: reset { 347 compatible = "socionext,uniphier-sld8-reset"; 348 #reset-cells = <1>; 349 }; 350 }; 351 352 nand: nand@68000000 { 353 compatible = "socionext,uniphier-denali-nand-v5a"; 354 status = "disabled"; 355 reg-names = "nand_data", "denali_reg"; 356 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 357 interrupts = <0 65 4>; 358 pinctrl-names = "default"; 359 pinctrl-0 = <&pinctrl_nand2cs>; 360 clocks = <&sys_clk 2>; 361 }; 362 }; 363}; 364 365#include "uniphier-pinctrl.dtsi" 366