1/* 2 * Device Tree Source for UniPhier sLD8 SoC 3 * 4 * Copyright (C) 2015-2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 */ 9 10/ { 11 compatible = "socionext,uniphier-sld8"; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu@0 { 20 device_type = "cpu"; 21 compatible = "arm,cortex-a9"; 22 reg = <0>; 23 enable-method = "psci"; 24 next-level-cache = <&l2>; 25 }; 26 }; 27 28 psci { 29 compatible = "arm,psci-0.2"; 30 method = "smc"; 31 }; 32 33 clocks { 34 refclk: ref { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <25000000>; 38 }; 39 40 arm_timer_clk: arm_timer_clk { 41 #clock-cells = <0>; 42 compatible = "fixed-clock"; 43 clock-frequency = <50000000>; 44 }; 45 }; 46 47 soc { 48 compatible = "simple-bus"; 49 #address-cells = <1>; 50 #size-cells = <1>; 51 ranges; 52 interrupt-parent = <&intc>; 53 u-boot,dm-pre-reloc; 54 55 l2: l2-cache@500c0000 { 56 compatible = "socionext,uniphier-system-cache"; 57 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, 58 <0x506c0000 0x400>; 59 interrupts = <0 174 4>, <0 175 4>; 60 cache-unified; 61 cache-size = <(256 * 1024)>; 62 cache-sets = <256>; 63 cache-line-size = <128>; 64 cache-level = <2>; 65 }; 66 67 serial0: serial@54006800 { 68 compatible = "socionext,uniphier-uart"; 69 status = "disabled"; 70 reg = <0x54006800 0x40>; 71 interrupts = <0 33 4>; 72 pinctrl-names = "default"; 73 pinctrl-0 = <&pinctrl_uart0>; 74 clocks = <&peri_clk 0>; 75 clock-frequency = <80000000>; 76 }; 77 78 serial1: serial@54006900 { 79 compatible = "socionext,uniphier-uart"; 80 status = "disabled"; 81 reg = <0x54006900 0x40>; 82 interrupts = <0 35 4>; 83 pinctrl-names = "default"; 84 pinctrl-0 = <&pinctrl_uart1>; 85 clocks = <&peri_clk 1>; 86 clock-frequency = <80000000>; 87 }; 88 89 serial2: serial@54006a00 { 90 compatible = "socionext,uniphier-uart"; 91 status = "disabled"; 92 reg = <0x54006a00 0x40>; 93 interrupts = <0 37 4>; 94 pinctrl-names = "default"; 95 pinctrl-0 = <&pinctrl_uart2>; 96 clocks = <&peri_clk 2>; 97 clock-frequency = <80000000>; 98 }; 99 100 serial3: serial@54006b00 { 101 compatible = "socionext,uniphier-uart"; 102 status = "disabled"; 103 reg = <0x54006b00 0x40>; 104 interrupts = <0 29 4>; 105 pinctrl-names = "default"; 106 pinctrl-0 = <&pinctrl_uart3>; 107 clocks = <&peri_clk 3>; 108 clock-frequency = <80000000>; 109 }; 110 111 port0x: gpio@55000008 { 112 compatible = "socionext,uniphier-gpio"; 113 reg = <0x55000008 0x8>; 114 gpio-controller; 115 #gpio-cells = <2>; 116 }; 117 118 port1x: gpio@55000010 { 119 compatible = "socionext,uniphier-gpio"; 120 reg = <0x55000010 0x8>; 121 gpio-controller; 122 #gpio-cells = <2>; 123 }; 124 125 port2x: gpio@55000018 { 126 compatible = "socionext,uniphier-gpio"; 127 reg = <0x55000018 0x8>; 128 gpio-controller; 129 #gpio-cells = <2>; 130 }; 131 132 port3x: gpio@55000020 { 133 compatible = "socionext,uniphier-gpio"; 134 reg = <0x55000020 0x8>; 135 gpio-controller; 136 #gpio-cells = <2>; 137 }; 138 139 port4: gpio@55000028 { 140 compatible = "socionext,uniphier-gpio"; 141 reg = <0x55000028 0x8>; 142 gpio-controller; 143 #gpio-cells = <2>; 144 }; 145 146 port5x: gpio@55000030 { 147 compatible = "socionext,uniphier-gpio"; 148 reg = <0x55000030 0x8>; 149 gpio-controller; 150 #gpio-cells = <2>; 151 }; 152 153 port6x: gpio@55000038 { 154 compatible = "socionext,uniphier-gpio"; 155 reg = <0x55000038 0x8>; 156 gpio-controller; 157 #gpio-cells = <2>; 158 }; 159 160 port7x: gpio@55000040 { 161 compatible = "socionext,uniphier-gpio"; 162 reg = <0x55000040 0x8>; 163 gpio-controller; 164 #gpio-cells = <2>; 165 }; 166 167 port8x: gpio@55000048 { 168 compatible = "socionext,uniphier-gpio"; 169 reg = <0x55000048 0x8>; 170 gpio-controller; 171 #gpio-cells = <2>; 172 }; 173 174 port9x: gpio@55000050 { 175 compatible = "socionext,uniphier-gpio"; 176 reg = <0x55000050 0x8>; 177 gpio-controller; 178 #gpio-cells = <2>; 179 }; 180 181 port10x: gpio@55000058 { 182 compatible = "socionext,uniphier-gpio"; 183 reg = <0x55000058 0x8>; 184 gpio-controller; 185 #gpio-cells = <2>; 186 }; 187 188 port11x: gpio@55000060 { 189 compatible = "socionext,uniphier-gpio"; 190 reg = <0x55000060 0x8>; 191 gpio-controller; 192 #gpio-cells = <2>; 193 }; 194 195 port12x: gpio@55000068 { 196 compatible = "socionext,uniphier-gpio"; 197 reg = <0x55000068 0x8>; 198 gpio-controller; 199 #gpio-cells = <2>; 200 }; 201 202 port13x: gpio@55000070 { 203 compatible = "socionext,uniphier-gpio"; 204 reg = <0x55000070 0x8>; 205 gpio-controller; 206 #gpio-cells = <2>; 207 }; 208 209 port14x: gpio@55000078 { 210 compatible = "socionext,uniphier-gpio"; 211 reg = <0x55000078 0x8>; 212 gpio-controller; 213 #gpio-cells = <2>; 214 }; 215 216 port16x: gpio@55000088 { 217 compatible = "socionext,uniphier-gpio"; 218 reg = <0x55000088 0x8>; 219 gpio-controller; 220 #gpio-cells = <2>; 221 }; 222 223 i2c0: i2c@58400000 { 224 compatible = "socionext,uniphier-i2c"; 225 status = "disabled"; 226 reg = <0x58400000 0x40>; 227 #address-cells = <1>; 228 #size-cells = <0>; 229 interrupts = <0 41 1>; 230 pinctrl-names = "default"; 231 pinctrl-0 = <&pinctrl_i2c0>; 232 clocks = <&peri_clk 4>; 233 clock-frequency = <100000>; 234 }; 235 236 i2c1: i2c@58480000 { 237 compatible = "socionext,uniphier-i2c"; 238 status = "disabled"; 239 reg = <0x58480000 0x40>; 240 #address-cells = <1>; 241 #size-cells = <0>; 242 interrupts = <0 42 1>; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&pinctrl_i2c1>; 245 clocks = <&peri_clk 5>; 246 clock-frequency = <100000>; 247 }; 248 249 /* chip-internal connection for DMD */ 250 i2c2: i2c@58500000 { 251 compatible = "socionext,uniphier-i2c"; 252 reg = <0x58500000 0x40>; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 interrupts = <0 43 1>; 256 pinctrl-names = "default"; 257 pinctrl-0 = <&pinctrl_i2c2>; 258 clocks = <&peri_clk 6>; 259 clock-frequency = <400000>; 260 }; 261 262 i2c3: i2c@58580000 { 263 compatible = "socionext,uniphier-i2c"; 264 status = "disabled"; 265 reg = <0x58580000 0x40>; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 interrupts = <0 44 1>; 269 pinctrl-names = "default"; 270 pinctrl-0 = <&pinctrl_i2c3>; 271 clocks = <&peri_clk 7>; 272 clock-frequency = <100000>; 273 }; 274 275 system_bus: system-bus@58c00000 { 276 compatible = "socionext,uniphier-system-bus"; 277 status = "disabled"; 278 reg = <0x58c00000 0x400>; 279 #address-cells = <2>; 280 #size-cells = <1>; 281 pinctrl-names = "default"; 282 pinctrl-0 = <&pinctrl_system_bus>; 283 }; 284 285 smpctrl@59801000 { 286 compatible = "socionext,uniphier-smpctrl"; 287 reg = <0x59801000 0x400>; 288 }; 289 290 mioctrl@59810000 { 291 compatible = "socionext,uniphier-sld8-mioctrl", 292 "simple-mfd", "syscon"; 293 reg = <0x59810000 0x800>; 294 295 mio_clk: clock { 296 compatible = "socionext,uniphier-sld8-mio-clock"; 297 #clock-cells = <1>; 298 }; 299 300 mio_rst: reset { 301 compatible = "socionext,uniphier-sld8-mio-reset"; 302 #reset-cells = <1>; 303 }; 304 }; 305 306 perictrl@59820000 { 307 compatible = "socionext,uniphier-sld8-perictrl", 308 "simple-mfd", "syscon"; 309 reg = <0x59820000 0x200>; 310 311 peri_clk: clock { 312 compatible = "socionext,uniphier-sld8-peri-clock"; 313 #clock-cells = <1>; 314 }; 315 316 peri_rst: reset { 317 compatible = "socionext,uniphier-sld8-peri-reset"; 318 #reset-cells = <1>; 319 }; 320 }; 321 322 sd: sdhc@5a400000 { 323 compatible = "socionext,uniphier-sdhc"; 324 status = "disabled"; 325 reg = <0x5a400000 0x200>; 326 interrupts = <0 76 4>; 327 pinctrl-names = "default", "1.8v"; 328 pinctrl-0 = <&pinctrl_sd>; 329 pinctrl-1 = <&pinctrl_sd_1v8>; 330 clocks = <&mio_clk 0>; 331 reset-names = "host", "bridge"; 332 resets = <&mio_rst 0>, <&mio_rst 3>; 333 bus-width = <4>; 334 cap-sd-highspeed; 335 sd-uhs-sdr12; 336 sd-uhs-sdr25; 337 sd-uhs-sdr50; 338 }; 339 340 emmc: sdhc@5a500000 { 341 compatible = "socionext,uniphier-sdhc"; 342 status = "disabled"; 343 reg = <0x5a500000 0x200>; 344 interrupts = <0 78 4>; 345 pinctrl-names = "default", "1.8v"; 346 pinctrl-0 = <&pinctrl_emmc>; 347 pinctrl-1 = <&pinctrl_emmc_1v8>; 348 clocks = <&mio_clk 1>; 349 reset-names = "host", "bridge"; 350 resets = <&mio_rst 1>, <&mio_rst 4>; 351 bus-width = <8>; 352 non-removable; 353 cap-mmc-highspeed; 354 cap-mmc-hw-reset; 355 }; 356 357 usb0: usb@5a800100 { 358 compatible = "socionext,uniphier-ehci", "generic-ehci"; 359 status = "disabled"; 360 reg = <0x5a800100 0x100>; 361 interrupts = <0 80 4>; 362 pinctrl-names = "default"; 363 pinctrl-0 = <&pinctrl_usb0>; 364 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; 365 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 366 <&mio_rst 12>; 367 }; 368 369 usb1: usb@5a810100 { 370 compatible = "socionext,uniphier-ehci", "generic-ehci"; 371 status = "disabled"; 372 reg = <0x5a810100 0x100>; 373 interrupts = <0 81 4>; 374 pinctrl-names = "default"; 375 pinctrl-0 = <&pinctrl_usb1>; 376 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; 377 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 378 <&mio_rst 13>; 379 }; 380 381 usb2: usb@5a820100 { 382 compatible = "socionext,uniphier-ehci", "generic-ehci"; 383 status = "disabled"; 384 reg = <0x5a820100 0x100>; 385 interrupts = <0 82 4>; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&pinctrl_usb2>; 388 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; 389 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, 390 <&mio_rst 14>; 391 }; 392 393 soc-glue@5f800000 { 394 compatible = "socionext,uniphier-sld8-soc-glue", 395 "simple-mfd", "syscon"; 396 reg = <0x5f800000 0x2000>; 397 u-boot,dm-pre-reloc; 398 399 pinctrl: pinctrl { 400 compatible = "socionext,uniphier-sld8-pinctrl"; 401 u-boot,dm-pre-reloc; 402 }; 403 }; 404 405 timer@60000200 { 406 compatible = "arm,cortex-a9-global-timer"; 407 reg = <0x60000200 0x20>; 408 interrupts = <1 11 0x104>; 409 clocks = <&arm_timer_clk>; 410 }; 411 412 timer@60000600 { 413 compatible = "arm,cortex-a9-twd-timer"; 414 reg = <0x60000600 0x20>; 415 interrupts = <1 13 0x104>; 416 clocks = <&arm_timer_clk>; 417 }; 418 419 intc: interrupt-controller@60001000 { 420 compatible = "arm,cortex-a9-gic"; 421 reg = <0x60001000 0x1000>, 422 <0x60000100 0x100>; 423 #interrupt-cells = <3>; 424 interrupt-controller; 425 }; 426 427 aidet: aidet@61830000 { 428 compatible = "socionext,uniphier-sld8-aidet"; 429 reg = <0x61830000 0x200>; 430 interrupt-controller; 431 #interrupt-cells = <2>; 432 }; 433 434 sysctrl@61840000 { 435 compatible = "socionext,uniphier-sld8-sysctrl", 436 "simple-mfd", "syscon"; 437 reg = <0x61840000 0x10000>; 438 439 sys_clk: clock { 440 compatible = "socionext,uniphier-sld8-clock"; 441 #clock-cells = <1>; 442 }; 443 444 sys_rst: reset { 445 compatible = "socionext,uniphier-sld8-reset"; 446 #reset-cells = <1>; 447 }; 448 }; 449 450 nand: nand@68000000 { 451 compatible = "socionext,uniphier-denali-nand-v5a"; 452 status = "disabled"; 453 reg-names = "nand_data", "denali_reg"; 454 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 455 interrupts = <0 65 4>; 456 pinctrl-names = "default"; 457 pinctrl-0 = <&pinctrl_nand2cs>; 458 clocks = <&sys_clk 2>; 459 }; 460 }; 461}; 462 463#include "uniphier-pinctrl.dtsi" 464