1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Device Tree Source for UniPhier sLD8 SoC 4// 5// Copyright (C) 2015-2016 Socionext Inc. 6// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 8#include <dt-bindings/gpio/uniphier-gpio.h> 9 10/ { 11 compatible = "socionext,uniphier-sld8"; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu@0 { 20 device_type = "cpu"; 21 compatible = "arm,cortex-a9"; 22 reg = <0>; 23 enable-method = "psci"; 24 next-level-cache = <&l2>; 25 }; 26 }; 27 28 psci { 29 compatible = "arm,psci-0.2"; 30 method = "smc"; 31 }; 32 33 clocks { 34 refclk: ref { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <25000000>; 38 }; 39 40 arm_timer_clk: arm-timer { 41 #clock-cells = <0>; 42 compatible = "fixed-clock"; 43 clock-frequency = <50000000>; 44 }; 45 }; 46 47 soc { 48 compatible = "simple-bus"; 49 #address-cells = <1>; 50 #size-cells = <1>; 51 ranges; 52 interrupt-parent = <&intc>; 53 54 l2: l2-cache@500c0000 { 55 compatible = "socionext,uniphier-system-cache"; 56 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, 57 <0x506c0000 0x400>; 58 interrupts = <0 174 4>, <0 175 4>; 59 cache-unified; 60 cache-size = <(256 * 1024)>; 61 cache-sets = <256>; 62 cache-line-size = <128>; 63 cache-level = <2>; 64 }; 65 66 serial0: serial@54006800 { 67 compatible = "socionext,uniphier-uart"; 68 status = "disabled"; 69 reg = <0x54006800 0x40>; 70 interrupts = <0 33 4>; 71 pinctrl-names = "default"; 72 pinctrl-0 = <&pinctrl_uart0>; 73 clocks = <&peri_clk 0>; 74 resets = <&peri_rst 0>; 75 }; 76 77 serial1: serial@54006900 { 78 compatible = "socionext,uniphier-uart"; 79 status = "disabled"; 80 reg = <0x54006900 0x40>; 81 interrupts = <0 35 4>; 82 pinctrl-names = "default"; 83 pinctrl-0 = <&pinctrl_uart1>; 84 clocks = <&peri_clk 1>; 85 resets = <&peri_rst 1>; 86 }; 87 88 serial2: serial@54006a00 { 89 compatible = "socionext,uniphier-uart"; 90 status = "disabled"; 91 reg = <0x54006a00 0x40>; 92 interrupts = <0 37 4>; 93 pinctrl-names = "default"; 94 pinctrl-0 = <&pinctrl_uart2>; 95 clocks = <&peri_clk 2>; 96 resets = <&peri_rst 2>; 97 }; 98 99 serial3: serial@54006b00 { 100 compatible = "socionext,uniphier-uart"; 101 status = "disabled"; 102 reg = <0x54006b00 0x40>; 103 interrupts = <0 29 4>; 104 pinctrl-names = "default"; 105 pinctrl-0 = <&pinctrl_uart3>; 106 clocks = <&peri_clk 3>; 107 resets = <&peri_rst 3>; 108 }; 109 110 gpio: gpio@55000000 { 111 compatible = "socionext,uniphier-gpio"; 112 reg = <0x55000000 0x200>; 113 interrupt-parent = <&aidet>; 114 interrupt-controller; 115 #interrupt-cells = <2>; 116 gpio-controller; 117 #gpio-cells = <2>; 118 gpio-ranges = <&pinctrl 0 0 0>, 119 <&pinctrl 104 0 0>, 120 <&pinctrl 112 0 0>; 121 gpio-ranges-group-names = "gpio_range0", 122 "gpio_range1", 123 "gpio_range2"; 124 ngpios = <136>; 125 socionext,interrupt-ranges = <0 48 13>, <14 62 2>; 126 }; 127 128 i2c0: i2c@58400000 { 129 compatible = "socionext,uniphier-i2c"; 130 status = "disabled"; 131 reg = <0x58400000 0x40>; 132 #address-cells = <1>; 133 #size-cells = <0>; 134 interrupts = <0 41 1>; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&pinctrl_i2c0>; 137 clocks = <&peri_clk 4>; 138 resets = <&peri_rst 4>; 139 clock-frequency = <100000>; 140 }; 141 142 i2c1: i2c@58480000 { 143 compatible = "socionext,uniphier-i2c"; 144 status = "disabled"; 145 reg = <0x58480000 0x40>; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 interrupts = <0 42 1>; 149 pinctrl-names = "default"; 150 pinctrl-0 = <&pinctrl_i2c1>; 151 clocks = <&peri_clk 5>; 152 resets = <&peri_rst 5>; 153 clock-frequency = <100000>; 154 }; 155 156 /* chip-internal connection for DMD */ 157 i2c2: i2c@58500000 { 158 compatible = "socionext,uniphier-i2c"; 159 reg = <0x58500000 0x40>; 160 #address-cells = <1>; 161 #size-cells = <0>; 162 interrupts = <0 43 1>; 163 pinctrl-names = "default"; 164 pinctrl-0 = <&pinctrl_i2c2>; 165 clocks = <&peri_clk 6>; 166 resets = <&peri_rst 6>; 167 clock-frequency = <400000>; 168 }; 169 170 i2c3: i2c@58580000 { 171 compatible = "socionext,uniphier-i2c"; 172 status = "disabled"; 173 reg = <0x58580000 0x40>; 174 #address-cells = <1>; 175 #size-cells = <0>; 176 interrupts = <0 44 1>; 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_i2c3>; 179 clocks = <&peri_clk 7>; 180 resets = <&peri_rst 7>; 181 clock-frequency = <100000>; 182 }; 183 184 system_bus: system-bus@58c00000 { 185 compatible = "socionext,uniphier-system-bus"; 186 status = "disabled"; 187 reg = <0x58c00000 0x400>; 188 #address-cells = <2>; 189 #size-cells = <1>; 190 pinctrl-names = "default"; 191 pinctrl-0 = <&pinctrl_system_bus>; 192 }; 193 194 smpctrl@59801000 { 195 compatible = "socionext,uniphier-smpctrl"; 196 reg = <0x59801000 0x400>; 197 }; 198 199 mioctrl@59810000 { 200 compatible = "socionext,uniphier-sld8-mioctrl", 201 "simple-mfd", "syscon"; 202 reg = <0x59810000 0x800>; 203 204 mio_clk: clock { 205 compatible = "socionext,uniphier-sld8-mio-clock"; 206 #clock-cells = <1>; 207 }; 208 209 mio_rst: reset { 210 compatible = "socionext,uniphier-sld8-mio-reset"; 211 #reset-cells = <1>; 212 }; 213 }; 214 215 perictrl@59820000 { 216 compatible = "socionext,uniphier-sld8-perictrl", 217 "simple-mfd", "syscon"; 218 reg = <0x59820000 0x200>; 219 220 peri_clk: clock { 221 compatible = "socionext,uniphier-sld8-peri-clock"; 222 #clock-cells = <1>; 223 }; 224 225 peri_rst: reset { 226 compatible = "socionext,uniphier-sld8-peri-reset"; 227 #reset-cells = <1>; 228 }; 229 }; 230 231 sd: sdhc@5a400000 { 232 compatible = "socionext,uniphier-sdhc"; 233 status = "disabled"; 234 reg = <0x5a400000 0x200>; 235 interrupts = <0 76 4>; 236 pinctrl-names = "default", "1.8v"; 237 pinctrl-0 = <&pinctrl_sd>; 238 pinctrl-1 = <&pinctrl_sd_1v8>; 239 clocks = <&mio_clk 0>; 240 reset-names = "host", "bridge"; 241 resets = <&mio_rst 0>, <&mio_rst 3>; 242 bus-width = <4>; 243 cap-sd-highspeed; 244 sd-uhs-sdr12; 245 sd-uhs-sdr25; 246 sd-uhs-sdr50; 247 }; 248 249 emmc: sdhc@5a500000 { 250 compatible = "socionext,uniphier-sdhc"; 251 status = "disabled"; 252 reg = <0x5a500000 0x200>; 253 interrupts = <0 78 4>; 254 pinctrl-names = "default", "1.8v"; 255 pinctrl-0 = <&pinctrl_emmc>; 256 pinctrl-1 = <&pinctrl_emmc_1v8>; 257 clocks = <&mio_clk 1>; 258 reset-names = "host", "bridge"; 259 resets = <&mio_rst 1>, <&mio_rst 4>; 260 bus-width = <8>; 261 non-removable; 262 cap-mmc-highspeed; 263 cap-mmc-hw-reset; 264 }; 265 266 usb0: usb@5a800100 { 267 compatible = "socionext,uniphier-ehci", "generic-ehci"; 268 status = "disabled"; 269 reg = <0x5a800100 0x100>; 270 interrupts = <0 80 4>; 271 pinctrl-names = "default"; 272 pinctrl-0 = <&pinctrl_usb0>; 273 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, 274 <&mio_clk 12>; 275 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 276 <&mio_rst 12>; 277 has-transaction-translator; 278 }; 279 280 usb1: usb@5a810100 { 281 compatible = "socionext,uniphier-ehci", "generic-ehci"; 282 status = "disabled"; 283 reg = <0x5a810100 0x100>; 284 interrupts = <0 81 4>; 285 pinctrl-names = "default"; 286 pinctrl-0 = <&pinctrl_usb1>; 287 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, 288 <&mio_clk 13>; 289 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 290 <&mio_rst 13>; 291 has-transaction-translator; 292 }; 293 294 usb2: usb@5a820100 { 295 compatible = "socionext,uniphier-ehci", "generic-ehci"; 296 status = "disabled"; 297 reg = <0x5a820100 0x100>; 298 interrupts = <0 82 4>; 299 pinctrl-names = "default"; 300 pinctrl-0 = <&pinctrl_usb2>; 301 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, 302 <&mio_clk 14>; 303 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, 304 <&mio_rst 14>; 305 has-transaction-translator; 306 }; 307 308 soc-glue@5f800000 { 309 compatible = "socionext,uniphier-sld8-soc-glue", 310 "simple-mfd", "syscon"; 311 reg = <0x5f800000 0x2000>; 312 313 pinctrl: pinctrl { 314 compatible = "socionext,uniphier-sld8-pinctrl"; 315 }; 316 }; 317 318 soc-glue@5f900000 { 319 compatible = "socionext,uniphier-sld8-soc-glue-debug", 320 "simple-mfd"; 321 #address-cells = <1>; 322 #size-cells = <1>; 323 ranges = <0 0x5f900000 0x2000>; 324 325 efuse@100 { 326 compatible = "socionext,uniphier-efuse"; 327 reg = <0x100 0x28>; 328 }; 329 330 efuse@200 { 331 compatible = "socionext,uniphier-efuse"; 332 reg = <0x200 0x14>; 333 }; 334 }; 335 336 timer@60000200 { 337 compatible = "arm,cortex-a9-global-timer"; 338 reg = <0x60000200 0x20>; 339 interrupts = <1 11 0x104>; 340 clocks = <&arm_timer_clk>; 341 }; 342 343 timer@60000600 { 344 compatible = "arm,cortex-a9-twd-timer"; 345 reg = <0x60000600 0x20>; 346 interrupts = <1 13 0x104>; 347 clocks = <&arm_timer_clk>; 348 }; 349 350 intc: interrupt-controller@60001000 { 351 compatible = "arm,cortex-a9-gic"; 352 reg = <0x60001000 0x1000>, 353 <0x60000100 0x100>; 354 #interrupt-cells = <3>; 355 interrupt-controller; 356 }; 357 358 aidet: aidet@61830000 { 359 compatible = "socionext,uniphier-sld8-aidet"; 360 reg = <0x61830000 0x200>; 361 interrupt-controller; 362 #interrupt-cells = <2>; 363 }; 364 365 sysctrl@61840000 { 366 compatible = "socionext,uniphier-sld8-sysctrl", 367 "simple-mfd", "syscon"; 368 reg = <0x61840000 0x10000>; 369 370 sys_clk: clock { 371 compatible = "socionext,uniphier-sld8-clock"; 372 #clock-cells = <1>; 373 }; 374 375 sys_rst: reset { 376 compatible = "socionext,uniphier-sld8-reset"; 377 #reset-cells = <1>; 378 }; 379 }; 380 381 nand: nand@68000000 { 382 compatible = "socionext,uniphier-denali-nand-v5a"; 383 status = "disabled"; 384 reg-names = "nand_data", "denali_reg"; 385 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 386 interrupts = <0 65 4>; 387 pinctrl-names = "default"; 388 pinctrl-0 = <&pinctrl_nand2cs>; 389 clocks = <&sys_clk 2>; 390 resets = <&sys_rst 2>; 391 }; 392 }; 393}; 394 395#include "uniphier-pinctrl.dtsi" 396