152159d27SMasahiro Yamada/* 252159d27SMasahiro Yamada * Device Tree Source for UniPhier sLD8 SoC 352159d27SMasahiro Yamada * 452159d27SMasahiro Yamada * Copyright (C) 2015-2016 Socionext Inc. 552159d27SMasahiro Yamada * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 652159d27SMasahiro Yamada * 7d9403001SMasahiro Yamada * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 852159d27SMasahiro Yamada */ 952159d27SMasahiro Yamada 10b443fb42SMasahiro Yamada#include <dt-bindings/gpio/uniphier-gpio.h> 11b443fb42SMasahiro Yamada 1252159d27SMasahiro Yamada/ { 1352159d27SMasahiro Yamada compatible = "socionext,uniphier-sld8"; 14f16eda96SMasahiro Yamada #address-cells = <1>; 15f16eda96SMasahiro Yamada #size-cells = <1>; 1652159d27SMasahiro Yamada 1752159d27SMasahiro Yamada cpus { 1852159d27SMasahiro Yamada #address-cells = <1>; 1952159d27SMasahiro Yamada #size-cells = <0>; 2052159d27SMasahiro Yamada 2152159d27SMasahiro Yamada cpu@0 { 2252159d27SMasahiro Yamada device_type = "cpu"; 2352159d27SMasahiro Yamada compatible = "arm,cortex-a9"; 2452159d27SMasahiro Yamada reg = <0>; 2552159d27SMasahiro Yamada enable-method = "psci"; 2652159d27SMasahiro Yamada next-level-cache = <&l2>; 2752159d27SMasahiro Yamada }; 2852159d27SMasahiro Yamada }; 2952159d27SMasahiro Yamada 30cd62214dSMasahiro Yamada psci { 31cd62214dSMasahiro Yamada compatible = "arm,psci-0.2"; 32cd62214dSMasahiro Yamada method = "smc"; 33cd62214dSMasahiro Yamada }; 34cd62214dSMasahiro Yamada 3552159d27SMasahiro Yamada clocks { 36cd62214dSMasahiro Yamada refclk: ref { 37cd62214dSMasahiro Yamada compatible = "fixed-clock"; 38cd62214dSMasahiro Yamada #clock-cells = <0>; 39cd62214dSMasahiro Yamada clock-frequency = <25000000>; 40cd62214dSMasahiro Yamada }; 41cd62214dSMasahiro Yamada 42b443fb42SMasahiro Yamada arm_timer_clk: arm-timer { 4352159d27SMasahiro Yamada #clock-cells = <0>; 4452159d27SMasahiro Yamada compatible = "fixed-clock"; 4552159d27SMasahiro Yamada clock-frequency = <50000000>; 4652159d27SMasahiro Yamada }; 4752159d27SMasahiro Yamada }; 4852159d27SMasahiro Yamada 49cd62214dSMasahiro Yamada soc { 50cd62214dSMasahiro Yamada compatible = "simple-bus"; 51cd62214dSMasahiro Yamada #address-cells = <1>; 52cd62214dSMasahiro Yamada #size-cells = <1>; 53cd62214dSMasahiro Yamada ranges; 54cd62214dSMasahiro Yamada interrupt-parent = <&intc>; 55cd62214dSMasahiro Yamada 5652159d27SMasahiro Yamada l2: l2-cache@500c0000 { 5752159d27SMasahiro Yamada compatible = "socionext,uniphier-system-cache"; 58cd62214dSMasahiro Yamada reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, 59cd62214dSMasahiro Yamada <0x506c0000 0x400>; 6052159d27SMasahiro Yamada interrupts = <0 174 4>, <0 175 4>; 6152159d27SMasahiro Yamada cache-unified; 6252159d27SMasahiro Yamada cache-size = <(256 * 1024)>; 6352159d27SMasahiro Yamada cache-sets = <256>; 6452159d27SMasahiro Yamada cache-line-size = <128>; 6552159d27SMasahiro Yamada cache-level = <2>; 6652159d27SMasahiro Yamada }; 6752159d27SMasahiro Yamada 68cd62214dSMasahiro Yamada serial0: serial@54006800 { 69cd62214dSMasahiro Yamada compatible = "socionext,uniphier-uart"; 70cd62214dSMasahiro Yamada status = "disabled"; 71cd62214dSMasahiro Yamada reg = <0x54006800 0x40>; 72cd62214dSMasahiro Yamada interrupts = <0 33 4>; 73cd62214dSMasahiro Yamada pinctrl-names = "default"; 74cd62214dSMasahiro Yamada pinctrl-0 = <&pinctrl_uart0>; 75cd62214dSMasahiro Yamada clocks = <&peri_clk 0>; 76cd62214dSMasahiro Yamada clock-frequency = <80000000>; 77b443fb42SMasahiro Yamada resets = <&peri_rst 0>; 78cd62214dSMasahiro Yamada }; 79cd62214dSMasahiro Yamada 80cd62214dSMasahiro Yamada serial1: serial@54006900 { 81cd62214dSMasahiro Yamada compatible = "socionext,uniphier-uart"; 82cd62214dSMasahiro Yamada status = "disabled"; 83cd62214dSMasahiro Yamada reg = <0x54006900 0x40>; 84cd62214dSMasahiro Yamada interrupts = <0 35 4>; 85cd62214dSMasahiro Yamada pinctrl-names = "default"; 86cd62214dSMasahiro Yamada pinctrl-0 = <&pinctrl_uart1>; 87cd62214dSMasahiro Yamada clocks = <&peri_clk 1>; 88cd62214dSMasahiro Yamada clock-frequency = <80000000>; 89b443fb42SMasahiro Yamada resets = <&peri_rst 1>; 90cd62214dSMasahiro Yamada }; 91cd62214dSMasahiro Yamada 92cd62214dSMasahiro Yamada serial2: serial@54006a00 { 93cd62214dSMasahiro Yamada compatible = "socionext,uniphier-uart"; 94cd62214dSMasahiro Yamada status = "disabled"; 95cd62214dSMasahiro Yamada reg = <0x54006a00 0x40>; 96cd62214dSMasahiro Yamada interrupts = <0 37 4>; 97cd62214dSMasahiro Yamada pinctrl-names = "default"; 98cd62214dSMasahiro Yamada pinctrl-0 = <&pinctrl_uart2>; 99cd62214dSMasahiro Yamada clocks = <&peri_clk 2>; 100cd62214dSMasahiro Yamada clock-frequency = <80000000>; 101b443fb42SMasahiro Yamada resets = <&peri_rst 2>; 102cd62214dSMasahiro Yamada }; 103cd62214dSMasahiro Yamada 104cd62214dSMasahiro Yamada serial3: serial@54006b00 { 105cd62214dSMasahiro Yamada compatible = "socionext,uniphier-uart"; 106cd62214dSMasahiro Yamada status = "disabled"; 107cd62214dSMasahiro Yamada reg = <0x54006b00 0x40>; 108cd62214dSMasahiro Yamada interrupts = <0 29 4>; 109cd62214dSMasahiro Yamada pinctrl-names = "default"; 110cd62214dSMasahiro Yamada pinctrl-0 = <&pinctrl_uart3>; 111cd62214dSMasahiro Yamada clocks = <&peri_clk 3>; 112cd62214dSMasahiro Yamada clock-frequency = <80000000>; 113b443fb42SMasahiro Yamada resets = <&peri_rst 3>; 114cd62214dSMasahiro Yamada }; 115cd62214dSMasahiro Yamada 1160f72b74bSMasahiro Yamada gpio: gpio@55000000 { 11752159d27SMasahiro Yamada compatible = "socionext,uniphier-gpio"; 1180f72b74bSMasahiro Yamada reg = <0x55000000 0x200>; 1190f72b74bSMasahiro Yamada interrupt-parent = <&aidet>; 1200f72b74bSMasahiro Yamada interrupt-controller; 1210f72b74bSMasahiro Yamada #interrupt-cells = <2>; 12252159d27SMasahiro Yamada gpio-controller; 12352159d27SMasahiro Yamada #gpio-cells = <2>; 1240f72b74bSMasahiro Yamada gpio-ranges = <&pinctrl 0 0 0>, 1250f72b74bSMasahiro Yamada <&pinctrl 104 0 0>, 1260f72b74bSMasahiro Yamada <&pinctrl 112 0 0>; 1270f72b74bSMasahiro Yamada gpio-ranges-group-names = "gpio_range0", 1280f72b74bSMasahiro Yamada "gpio_range1", 1290f72b74bSMasahiro Yamada "gpio_range2"; 1300f72b74bSMasahiro Yamada ngpios = <136>; 131b443fb42SMasahiro Yamada socionext,interrupt-ranges = <0 48 13>, <14 62 2>; 13252159d27SMasahiro Yamada }; 13352159d27SMasahiro Yamada 13452159d27SMasahiro Yamada i2c0: i2c@58400000 { 13552159d27SMasahiro Yamada compatible = "socionext,uniphier-i2c"; 13652159d27SMasahiro Yamada status = "disabled"; 13752159d27SMasahiro Yamada reg = <0x58400000 0x40>; 13852159d27SMasahiro Yamada #address-cells = <1>; 13952159d27SMasahiro Yamada #size-cells = <0>; 14052159d27SMasahiro Yamada interrupts = <0 41 1>; 14152159d27SMasahiro Yamada pinctrl-names = "default"; 14252159d27SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c0>; 143cd62214dSMasahiro Yamada clocks = <&peri_clk 4>; 144b443fb42SMasahiro Yamada resets = <&peri_rst 4>; 14552159d27SMasahiro Yamada clock-frequency = <100000>; 14652159d27SMasahiro Yamada }; 14752159d27SMasahiro Yamada 14852159d27SMasahiro Yamada i2c1: i2c@58480000 { 14952159d27SMasahiro Yamada compatible = "socionext,uniphier-i2c"; 15052159d27SMasahiro Yamada status = "disabled"; 15152159d27SMasahiro Yamada reg = <0x58480000 0x40>; 15252159d27SMasahiro Yamada #address-cells = <1>; 15352159d27SMasahiro Yamada #size-cells = <0>; 15452159d27SMasahiro Yamada interrupts = <0 42 1>; 15552159d27SMasahiro Yamada pinctrl-names = "default"; 15652159d27SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c1>; 157cd62214dSMasahiro Yamada clocks = <&peri_clk 5>; 158b443fb42SMasahiro Yamada resets = <&peri_rst 5>; 15952159d27SMasahiro Yamada clock-frequency = <100000>; 16052159d27SMasahiro Yamada }; 16152159d27SMasahiro Yamada 16252159d27SMasahiro Yamada /* chip-internal connection for DMD */ 16352159d27SMasahiro Yamada i2c2: i2c@58500000 { 16452159d27SMasahiro Yamada compatible = "socionext,uniphier-i2c"; 16552159d27SMasahiro Yamada reg = <0x58500000 0x40>; 16652159d27SMasahiro Yamada #address-cells = <1>; 16752159d27SMasahiro Yamada #size-cells = <0>; 16852159d27SMasahiro Yamada interrupts = <0 43 1>; 16952159d27SMasahiro Yamada pinctrl-names = "default"; 17052159d27SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c2>; 171cd62214dSMasahiro Yamada clocks = <&peri_clk 6>; 172b443fb42SMasahiro Yamada resets = <&peri_rst 6>; 17352159d27SMasahiro Yamada clock-frequency = <400000>; 17452159d27SMasahiro Yamada }; 17552159d27SMasahiro Yamada 17652159d27SMasahiro Yamada i2c3: i2c@58580000 { 17752159d27SMasahiro Yamada compatible = "socionext,uniphier-i2c"; 17852159d27SMasahiro Yamada status = "disabled"; 17952159d27SMasahiro Yamada reg = <0x58580000 0x40>; 18052159d27SMasahiro Yamada #address-cells = <1>; 18152159d27SMasahiro Yamada #size-cells = <0>; 18252159d27SMasahiro Yamada interrupts = <0 44 1>; 18352159d27SMasahiro Yamada pinctrl-names = "default"; 18452159d27SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c3>; 185cd62214dSMasahiro Yamada clocks = <&peri_clk 7>; 186b443fb42SMasahiro Yamada resets = <&peri_rst 7>; 18752159d27SMasahiro Yamada clock-frequency = <100000>; 18852159d27SMasahiro Yamada }; 18952159d27SMasahiro Yamada 190cd62214dSMasahiro Yamada system_bus: system-bus@58c00000 { 191cd62214dSMasahiro Yamada compatible = "socionext,uniphier-system-bus"; 192cd62214dSMasahiro Yamada status = "disabled"; 193cd62214dSMasahiro Yamada reg = <0x58c00000 0x400>; 194cd62214dSMasahiro Yamada #address-cells = <2>; 195cd62214dSMasahiro Yamada #size-cells = <1>; 196cd62214dSMasahiro Yamada pinctrl-names = "default"; 197cd62214dSMasahiro Yamada pinctrl-0 = <&pinctrl_system_bus>; 198cd62214dSMasahiro Yamada }; 199cd62214dSMasahiro Yamada 200abb6ac25SMasahiro Yamada smpctrl@59801000 { 201cd62214dSMasahiro Yamada compatible = "socionext,uniphier-smpctrl"; 202cd62214dSMasahiro Yamada reg = <0x59801000 0x400>; 203cd62214dSMasahiro Yamada }; 204cd62214dSMasahiro Yamada 205cd62214dSMasahiro Yamada mioctrl@59810000 { 206cd62214dSMasahiro Yamada compatible = "socionext,uniphier-sld8-mioctrl", 207cd62214dSMasahiro Yamada "simple-mfd", "syscon"; 208cd62214dSMasahiro Yamada reg = <0x59810000 0x800>; 209cd62214dSMasahiro Yamada 210cd62214dSMasahiro Yamada mio_clk: clock { 211cd62214dSMasahiro Yamada compatible = "socionext,uniphier-sld8-mio-clock"; 212cd62214dSMasahiro Yamada #clock-cells = <1>; 213cd62214dSMasahiro Yamada }; 214cd62214dSMasahiro Yamada 215cd62214dSMasahiro Yamada mio_rst: reset { 216cd62214dSMasahiro Yamada compatible = "socionext,uniphier-sld8-mio-reset"; 217cd62214dSMasahiro Yamada #reset-cells = <1>; 218cd62214dSMasahiro Yamada }; 219cd62214dSMasahiro Yamada }; 220cd62214dSMasahiro Yamada 221cd62214dSMasahiro Yamada perictrl@59820000 { 222cd62214dSMasahiro Yamada compatible = "socionext,uniphier-sld8-perictrl", 223cd62214dSMasahiro Yamada "simple-mfd", "syscon"; 224cd62214dSMasahiro Yamada reg = <0x59820000 0x200>; 225cd62214dSMasahiro Yamada 226cd62214dSMasahiro Yamada peri_clk: clock { 227cd62214dSMasahiro Yamada compatible = "socionext,uniphier-sld8-peri-clock"; 228cd62214dSMasahiro Yamada #clock-cells = <1>; 229cd62214dSMasahiro Yamada }; 230cd62214dSMasahiro Yamada 231cd62214dSMasahiro Yamada peri_rst: reset { 232cd62214dSMasahiro Yamada compatible = "socionext,uniphier-sld8-peri-reset"; 233cd62214dSMasahiro Yamada #reset-cells = <1>; 234cd62214dSMasahiro Yamada }; 235cd62214dSMasahiro Yamada }; 236cd62214dSMasahiro Yamada 23752159d27SMasahiro Yamada sd: sdhc@5a400000 { 23852159d27SMasahiro Yamada compatible = "socionext,uniphier-sdhc"; 23952159d27SMasahiro Yamada status = "disabled"; 24052159d27SMasahiro Yamada reg = <0x5a400000 0x200>; 24152159d27SMasahiro Yamada interrupts = <0 76 4>; 24252159d27SMasahiro Yamada pinctrl-names = "default", "1.8v"; 24352159d27SMasahiro Yamada pinctrl-0 = <&pinctrl_sd>; 24452159d27SMasahiro Yamada pinctrl-1 = <&pinctrl_sd_1v8>; 24552159d27SMasahiro Yamada clocks = <&mio_clk 0>; 24652159d27SMasahiro Yamada reset-names = "host", "bridge"; 24752159d27SMasahiro Yamada resets = <&mio_rst 0>, <&mio_rst 3>; 24852159d27SMasahiro Yamada bus-width = <4>; 249cd62214dSMasahiro Yamada cap-sd-highspeed; 250cd62214dSMasahiro Yamada sd-uhs-sdr12; 251cd62214dSMasahiro Yamada sd-uhs-sdr25; 252cd62214dSMasahiro Yamada sd-uhs-sdr50; 25352159d27SMasahiro Yamada }; 25452159d27SMasahiro Yamada 25552159d27SMasahiro Yamada emmc: sdhc@5a500000 { 25652159d27SMasahiro Yamada compatible = "socionext,uniphier-sdhc"; 25752159d27SMasahiro Yamada status = "disabled"; 25852159d27SMasahiro Yamada reg = <0x5a500000 0x200>; 259cd62214dSMasahiro Yamada interrupts = <0 78 4>; 26052159d27SMasahiro Yamada pinctrl-names = "default", "1.8v"; 26152159d27SMasahiro Yamada pinctrl-0 = <&pinctrl_emmc>; 26252159d27SMasahiro Yamada pinctrl-1 = <&pinctrl_emmc_1v8>; 26352159d27SMasahiro Yamada clocks = <&mio_clk 1>; 264cd62214dSMasahiro Yamada reset-names = "host", "bridge"; 265cd62214dSMasahiro Yamada resets = <&mio_rst 1>, <&mio_rst 4>; 26652159d27SMasahiro Yamada bus-width = <8>; 26752159d27SMasahiro Yamada non-removable; 268cd62214dSMasahiro Yamada cap-mmc-highspeed; 269cd62214dSMasahiro Yamada cap-mmc-hw-reset; 27052159d27SMasahiro Yamada }; 27152159d27SMasahiro Yamada 27252159d27SMasahiro Yamada usb0: usb@5a800100 { 27352159d27SMasahiro Yamada compatible = "socionext,uniphier-ehci", "generic-ehci"; 27452159d27SMasahiro Yamada status = "disabled"; 27552159d27SMasahiro Yamada reg = <0x5a800100 0x100>; 27652159d27SMasahiro Yamada interrupts = <0 80 4>; 27752159d27SMasahiro Yamada pinctrl-names = "default"; 27852159d27SMasahiro Yamada pinctrl-0 = <&pinctrl_usb0>; 279b443fb42SMasahiro Yamada clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, 280b443fb42SMasahiro Yamada <&mio_clk 12>; 28152159d27SMasahiro Yamada resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 28252159d27SMasahiro Yamada <&mio_rst 12>; 283*46820e3fSMasahiro Yamada has-transaction-translator; 28452159d27SMasahiro Yamada }; 28552159d27SMasahiro Yamada 28652159d27SMasahiro Yamada usb1: usb@5a810100 { 28752159d27SMasahiro Yamada compatible = "socionext,uniphier-ehci", "generic-ehci"; 28852159d27SMasahiro Yamada status = "disabled"; 28952159d27SMasahiro Yamada reg = <0x5a810100 0x100>; 29052159d27SMasahiro Yamada interrupts = <0 81 4>; 29152159d27SMasahiro Yamada pinctrl-names = "default"; 29252159d27SMasahiro Yamada pinctrl-0 = <&pinctrl_usb1>; 293b443fb42SMasahiro Yamada clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, 294b443fb42SMasahiro Yamada <&mio_clk 13>; 29552159d27SMasahiro Yamada resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 29652159d27SMasahiro Yamada <&mio_rst 13>; 297*46820e3fSMasahiro Yamada has-transaction-translator; 29852159d27SMasahiro Yamada }; 29952159d27SMasahiro Yamada 30052159d27SMasahiro Yamada usb2: usb@5a820100 { 30152159d27SMasahiro Yamada compatible = "socionext,uniphier-ehci", "generic-ehci"; 30252159d27SMasahiro Yamada status = "disabled"; 30352159d27SMasahiro Yamada reg = <0x5a820100 0x100>; 30452159d27SMasahiro Yamada interrupts = <0 82 4>; 30552159d27SMasahiro Yamada pinctrl-names = "default"; 30652159d27SMasahiro Yamada pinctrl-0 = <&pinctrl_usb2>; 307b443fb42SMasahiro Yamada clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, 308b443fb42SMasahiro Yamada <&mio_clk 14>; 30952159d27SMasahiro Yamada resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, 31052159d27SMasahiro Yamada <&mio_rst 14>; 311*46820e3fSMasahiro Yamada has-transaction-translator; 31252159d27SMasahiro Yamada }; 31352159d27SMasahiro Yamada 314cd62214dSMasahiro Yamada soc-glue@5f800000 { 315cd62214dSMasahiro Yamada compatible = "socionext,uniphier-sld8-soc-glue", 316cd62214dSMasahiro Yamada "simple-mfd", "syscon"; 317cd62214dSMasahiro Yamada reg = <0x5f800000 0x2000>; 318cd62214dSMasahiro Yamada 319cd62214dSMasahiro Yamada pinctrl: pinctrl { 320cd62214dSMasahiro Yamada compatible = "socionext,uniphier-sld8-pinctrl"; 321cd62214dSMasahiro Yamada }; 322cd62214dSMasahiro Yamada }; 323cd62214dSMasahiro Yamada 324*46820e3fSMasahiro Yamada soc-glue@5f900000 { 325*46820e3fSMasahiro Yamada compatible = "socionext,uniphier-sld8-soc-glue-debug", 326*46820e3fSMasahiro Yamada "simple-mfd"; 327*46820e3fSMasahiro Yamada #address-cells = <1>; 328*46820e3fSMasahiro Yamada #size-cells = <1>; 329*46820e3fSMasahiro Yamada ranges = <0 0x5f900000 0x2000>; 330*46820e3fSMasahiro Yamada 331*46820e3fSMasahiro Yamada efuse@100 { 332*46820e3fSMasahiro Yamada compatible = "socionext,uniphier-efuse"; 333*46820e3fSMasahiro Yamada reg = <0x100 0x28>; 334*46820e3fSMasahiro Yamada }; 335*46820e3fSMasahiro Yamada 336*46820e3fSMasahiro Yamada efuse@200 { 337*46820e3fSMasahiro Yamada compatible = "socionext,uniphier-efuse"; 338*46820e3fSMasahiro Yamada reg = <0x200 0x14>; 339*46820e3fSMasahiro Yamada }; 340*46820e3fSMasahiro Yamada }; 341*46820e3fSMasahiro Yamada 342cd62214dSMasahiro Yamada timer@60000200 { 343cd62214dSMasahiro Yamada compatible = "arm,cortex-a9-global-timer"; 344cd62214dSMasahiro Yamada reg = <0x60000200 0x20>; 345cd62214dSMasahiro Yamada interrupts = <1 11 0x104>; 346cd62214dSMasahiro Yamada clocks = <&arm_timer_clk>; 347cd62214dSMasahiro Yamada }; 348cd62214dSMasahiro Yamada 349cd62214dSMasahiro Yamada timer@60000600 { 350cd62214dSMasahiro Yamada compatible = "arm,cortex-a9-twd-timer"; 351cd62214dSMasahiro Yamada reg = <0x60000600 0x20>; 352cd62214dSMasahiro Yamada interrupts = <1 13 0x104>; 353cd62214dSMasahiro Yamada clocks = <&arm_timer_clk>; 354cd62214dSMasahiro Yamada }; 355cd62214dSMasahiro Yamada 356cd62214dSMasahiro Yamada intc: interrupt-controller@60001000 { 357cd62214dSMasahiro Yamada compatible = "arm,cortex-a9-gic"; 358cd62214dSMasahiro Yamada reg = <0x60001000 0x1000>, 359cd62214dSMasahiro Yamada <0x60000100 0x100>; 360cd62214dSMasahiro Yamada #interrupt-cells = <3>; 361cd62214dSMasahiro Yamada interrupt-controller; 362cd62214dSMasahiro Yamada }; 363cd62214dSMasahiro Yamada 3646c9e46efSMasahiro Yamada aidet: aidet@61830000 { 3656c9e46efSMasahiro Yamada compatible = "socionext,uniphier-sld8-aidet"; 36652159d27SMasahiro Yamada reg = <0x61830000 0x200>; 3676c9e46efSMasahiro Yamada interrupt-controller; 3686c9e46efSMasahiro Yamada #interrupt-cells = <2>; 36952159d27SMasahiro Yamada }; 37052159d27SMasahiro Yamada 371cd62214dSMasahiro Yamada sysctrl@61840000 { 372cd62214dSMasahiro Yamada compatible = "socionext,uniphier-sld8-sysctrl", 373cd62214dSMasahiro Yamada "simple-mfd", "syscon"; 374cd62214dSMasahiro Yamada reg = <0x61840000 0x10000>; 37552159d27SMasahiro Yamada 376cd62214dSMasahiro Yamada sys_clk: clock { 37752159d27SMasahiro Yamada compatible = "socionext,uniphier-sld8-clock"; 378cd62214dSMasahiro Yamada #clock-cells = <1>; 37952159d27SMasahiro Yamada }; 38052159d27SMasahiro Yamada 381cd62214dSMasahiro Yamada sys_rst: reset { 38252159d27SMasahiro Yamada compatible = "socionext,uniphier-sld8-reset"; 383cd62214dSMasahiro Yamada #reset-cells = <1>; 38452159d27SMasahiro Yamada }; 385cd62214dSMasahiro Yamada }; 386cd62214dSMasahiro Yamada 387cd62214dSMasahiro Yamada nand: nand@68000000 { 388abb6ac25SMasahiro Yamada compatible = "socionext,uniphier-denali-nand-v5a"; 389cd62214dSMasahiro Yamada status = "disabled"; 390cd62214dSMasahiro Yamada reg-names = "nand_data", "denali_reg"; 391cd62214dSMasahiro Yamada reg = <0x68000000 0x20>, <0x68100000 0x1000>; 392cd62214dSMasahiro Yamada interrupts = <0 65 4>; 393cd62214dSMasahiro Yamada pinctrl-names = "default"; 3946c9e46efSMasahiro Yamada pinctrl-0 = <&pinctrl_nand2cs>; 395cd62214dSMasahiro Yamada clocks = <&sys_clk 2>; 396b443fb42SMasahiro Yamada resets = <&sys_rst 2>; 397cd62214dSMasahiro Yamada }; 398cd62214dSMasahiro Yamada }; 399cd62214dSMasahiro Yamada}; 400cd62214dSMasahiro Yamada 4016c9e46efSMasahiro Yamada#include "uniphier-pinctrl.dtsi" 402