1/* 2 * Device Tree Source for UniPhier PXs3 SoC 3 * 4 * Copyright (C) 2017 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ X11 8 */ 9 10/memreserve/ 0x80000000 0x00080000; 11 12/ { 13 compatible = "socionext,uniphier-pxs3"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&gic>; 17 18 cpus { 19 #address-cells = <2>; 20 #size-cells = <0>; 21 22 cpu-map { 23 cluster0 { 24 core0 { 25 cpu = <&cpu0>; 26 }; 27 core1 { 28 cpu = <&cpu1>; 29 }; 30 core2 { 31 cpu = <&cpu2>; 32 }; 33 core3 { 34 cpu = <&cpu3>; 35 }; 36 }; 37 }; 38 39 cpu0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53", "arm,armv8"; 42 reg = <0 0x000>; 43 enable-method = "psci"; 44 }; 45 46 cpu1: cpu@1 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a53", "arm,armv8"; 49 reg = <0 0x001>; 50 enable-method = "psci"; 51 }; 52 53 cpu2: cpu@2 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53", "arm,armv8"; 56 reg = <0 0x002>; 57 enable-method = "psci"; 58 }; 59 60 cpu3: cpu@3 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53", "arm,armv8"; 63 reg = <0 0x003>; 64 enable-method = "psci"; 65 }; 66 }; 67 68 psci { 69 compatible = "arm,psci-1.0"; 70 method = "smc"; 71 }; 72 73 clocks { 74 refclk: ref { 75 compatible = "fixed-clock"; 76 #clock-cells = <0>; 77 clock-frequency = <25000000>; 78 }; 79 }; 80 81 timer { 82 compatible = "arm,armv8-timer"; 83 interrupts = <1 13 4>, 84 <1 14 4>, 85 <1 11 4>, 86 <1 10 4>; 87 }; 88 89 soc@0 { 90 compatible = "simple-bus"; 91 #address-cells = <1>; 92 #size-cells = <1>; 93 ranges = <0 0 0 0xffffffff>; 94 95 serial0: serial@54006800 { 96 compatible = "socionext,uniphier-uart"; 97 status = "disabled"; 98 reg = <0x54006800 0x40>; 99 interrupts = <0 33 4>; 100 pinctrl-names = "default"; 101 pinctrl-0 = <&pinctrl_uart0>; 102 clocks = <&peri_clk 0>; 103 clock-frequency = <58820000>; 104 }; 105 106 serial1: serial@54006900 { 107 compatible = "socionext,uniphier-uart"; 108 status = "disabled"; 109 reg = <0x54006900 0x40>; 110 interrupts = <0 35 4>; 111 pinctrl-names = "default"; 112 pinctrl-0 = <&pinctrl_uart1>; 113 clocks = <&peri_clk 1>; 114 clock-frequency = <58820000>; 115 }; 116 117 serial2: serial@54006a00 { 118 compatible = "socionext,uniphier-uart"; 119 status = "disabled"; 120 reg = <0x54006a00 0x40>; 121 interrupts = <0 37 4>; 122 pinctrl-names = "default"; 123 pinctrl-0 = <&pinctrl_uart2>; 124 clocks = <&peri_clk 2>; 125 clock-frequency = <58820000>; 126 }; 127 128 serial3: serial@54006b00 { 129 compatible = "socionext,uniphier-uart"; 130 status = "disabled"; 131 reg = <0x54006b00 0x40>; 132 interrupts = <0 177 4>; 133 pinctrl-names = "default"; 134 pinctrl-0 = <&pinctrl_uart3>; 135 clocks = <&peri_clk 3>; 136 clock-frequency = <58820000>; 137 }; 138 139 i2c0: i2c@58780000 { 140 compatible = "socionext,uniphier-fi2c"; 141 status = "disabled"; 142 reg = <0x58780000 0x80>; 143 #address-cells = <1>; 144 #size-cells = <0>; 145 interrupts = <0 41 4>; 146 pinctrl-names = "default"; 147 pinctrl-0 = <&pinctrl_i2c0>; 148 clocks = <&peri_clk 4>; 149 clock-frequency = <100000>; 150 }; 151 152 i2c1: i2c@58781000 { 153 compatible = "socionext,uniphier-fi2c"; 154 status = "disabled"; 155 reg = <0x58781000 0x80>; 156 #address-cells = <1>; 157 #size-cells = <0>; 158 interrupts = <0 42 4>; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&pinctrl_i2c1>; 161 clocks = <&peri_clk 5>; 162 clock-frequency = <100000>; 163 }; 164 165 i2c2: i2c@58782000 { 166 compatible = "socionext,uniphier-fi2c"; 167 status = "disabled"; 168 reg = <0x58782000 0x80>; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 interrupts = <0 43 4>; 172 clocks = <&peri_clk 6>; 173 clock-frequency = <100000>; 174 }; 175 176 i2c3: i2c@58783000 { 177 compatible = "socionext,uniphier-fi2c"; 178 status = "disabled"; 179 reg = <0x58783000 0x80>; 180 #address-cells = <1>; 181 #size-cells = <0>; 182 interrupts = <0 44 4>; 183 pinctrl-names = "default"; 184 pinctrl-0 = <&pinctrl_i2c3>; 185 clocks = <&peri_clk 7>; 186 clock-frequency = <100000>; 187 }; 188 189 /* chip-internal connection for HDMI */ 190 i2c6: i2c@58786000 { 191 compatible = "socionext,uniphier-fi2c"; 192 reg = <0x58786000 0x80>; 193 #address-cells = <1>; 194 #size-cells = <0>; 195 interrupts = <0 26 4>; 196 clocks = <&peri_clk 10>; 197 clock-frequency = <400000>; 198 }; 199 200 system_bus: system-bus@58c00000 { 201 compatible = "socionext,uniphier-system-bus"; 202 status = "disabled"; 203 reg = <0x58c00000 0x400>; 204 #address-cells = <2>; 205 #size-cells = <1>; 206 pinctrl-names = "default"; 207 pinctrl-0 = <&pinctrl_system_bus>; 208 }; 209 210 smpctrl@59800000 { 211 compatible = "socionext,uniphier-smpctrl"; 212 reg = <0x59801000 0x400>; 213 }; 214 215 sdctrl@59810000 { 216 compatible = "socionext,uniphier-pxs3-sdctrl", 217 "simple-mfd", "syscon"; 218 reg = <0x59810000 0x800>; 219 220 sd_clk: clock { 221 compatible = "socionext,uniphier-pxs3-sd-clock"; 222 #clock-cells = <1>; 223 }; 224 225 sd_rst: reset { 226 compatible = "socionext,uniphier-pxs3-sd-reset"; 227 #reset-cells = <1>; 228 }; 229 }; 230 231 perictrl@59820000 { 232 compatible = "socionext,uniphier-pxs3-perictrl", 233 "simple-mfd", "syscon"; 234 reg = <0x59820000 0x200>; 235 236 peri_clk: clock { 237 compatible = "socionext,uniphier-pxs3-peri-clock"; 238 #clock-cells = <1>; 239 }; 240 241 peri_rst: reset { 242 compatible = "socionext,uniphier-pxs3-peri-reset"; 243 #reset-cells = <1>; 244 }; 245 }; 246 247 emmc: sdhc@5a000000 { 248 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 249 status = "disabled"; 250 reg = <0x5a000000 0x400>; 251 interrupts = <0 78 4>; 252 pinctrl-names = "default"; 253 pinctrl-0 = <&pinctrl_emmc_1v8>; 254 clocks = <&sys_clk 4>; 255 bus-width = <8>; 256 mmc-ddr-1_8v; 257 mmc-hs200-1_8v; 258 }; 259 260 sd: sdhc@5a400000 { 261 compatible = "socionext,uniphier-sdhc"; 262 status = "disabled"; 263 reg = <0x5a400000 0x800>; 264 interrupts = <0 76 4>; 265 pinctrl-names = "default"; 266 pinctrl-0 = <&pinctrl_sd>; 267 clocks = <&sd_clk 0>; 268 reset-names = "host"; 269 resets = <&sd_rst 0>; 270 bus-width = <4>; 271 cap-sd-highspeed; 272 }; 273 274 soc-glue@5f800000 { 275 compatible = "socionext,uniphier-pxs3-soc-glue", 276 "simple-mfd", "syscon"; 277 reg = <0x5f800000 0x2000>; 278 279 pinctrl: pinctrl { 280 compatible = "socionext,uniphier-pxs3-pinctrl"; 281 }; 282 }; 283 284 aidet@5fc20000 { 285 compatible = "simple-mfd", "syscon"; 286 reg = <0x5fc20000 0x200>; 287 }; 288 289 gic: interrupt-controller@5fe00000 { 290 compatible = "arm,gic-v3"; 291 reg = <0x5fe00000 0x10000>, /* GICD */ 292 <0x5fe80000 0x80000>; /* GICR */ 293 interrupt-controller; 294 #interrupt-cells = <3>; 295 interrupts = <1 9 4>; 296 }; 297 298 sysctrl@61840000 { 299 compatible = "socionext,uniphier-pxs3-sysctrl", 300 "simple-mfd", "syscon"; 301 reg = <0x61840000 0x10000>; 302 303 sys_clk: clock { 304 compatible = "socionext,uniphier-pxs3-clock"; 305 #clock-cells = <1>; 306 }; 307 308 sys_rst: reset { 309 compatible = "socionext,uniphier-pxs3-reset"; 310 #reset-cells = <1>; 311 }; 312 }; 313 314 nand: nand@68000000 { 315 compatible = "socionext,denali-nand-v5b"; 316 status = "disabled"; 317 reg-names = "nand_data", "denali_reg"; 318 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 319 interrupts = <0 65 4>; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&pinctrl_nand>; 322 clocks = <&sys_clk 2>; 323 nand-ecc-strength = <8>; 324 }; 325 }; 326}; 327 328/include/ "uniphier-pinctrl.dtsi" 329