1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Device Tree Source for UniPhier PXs3 SoC 4// 5// Copyright (C) 2017 Socionext Inc. 6// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/gpio/uniphier-gpio.h> 10 11/memreserve/ 0x80000000 0x02000000; 12 13/ { 14 compatible = "socionext,uniphier-pxs3"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 interrupt-parent = <&gic>; 18 19 cpus { 20 #address-cells = <2>; 21 #size-cells = <0>; 22 23 cpu-map { 24 cluster0 { 25 core0 { 26 cpu = <&cpu0>; 27 }; 28 core1 { 29 cpu = <&cpu1>; 30 }; 31 core2 { 32 cpu = <&cpu2>; 33 }; 34 core3 { 35 cpu = <&cpu3>; 36 }; 37 }; 38 }; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53", "arm,armv8"; 43 reg = <0 0x000>; 44 clocks = <&sys_clk 33>; 45 enable-method = "psci"; 46 operating-points-v2 = <&cluster0_opp>; 47 }; 48 49 cpu1: cpu@1 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53", "arm,armv8"; 52 reg = <0 0x001>; 53 clocks = <&sys_clk 33>; 54 enable-method = "psci"; 55 operating-points-v2 = <&cluster0_opp>; 56 }; 57 58 cpu2: cpu@2 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a53", "arm,armv8"; 61 reg = <0 0x002>; 62 clocks = <&sys_clk 33>; 63 enable-method = "psci"; 64 operating-points-v2 = <&cluster0_opp>; 65 }; 66 67 cpu3: cpu@3 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a53", "arm,armv8"; 70 reg = <0 0x003>; 71 clocks = <&sys_clk 33>; 72 enable-method = "psci"; 73 operating-points-v2 = <&cluster0_opp>; 74 }; 75 }; 76 77 cluster0_opp: opp-table { 78 compatible = "operating-points-v2"; 79 opp-shared; 80 81 opp-250000000 { 82 opp-hz = /bits/ 64 <250000000>; 83 clock-latency-ns = <300>; 84 }; 85 opp-325000000 { 86 opp-hz = /bits/ 64 <325000000>; 87 clock-latency-ns = <300>; 88 }; 89 opp-500000000 { 90 opp-hz = /bits/ 64 <500000000>; 91 clock-latency-ns = <300>; 92 }; 93 opp-650000000 { 94 opp-hz = /bits/ 64 <650000000>; 95 clock-latency-ns = <300>; 96 }; 97 opp-666667000 { 98 opp-hz = /bits/ 64 <666667000>; 99 clock-latency-ns = <300>; 100 }; 101 opp-866667000 { 102 opp-hz = /bits/ 64 <866667000>; 103 clock-latency-ns = <300>; 104 }; 105 opp-1000000000 { 106 opp-hz = /bits/ 64 <1000000000>; 107 clock-latency-ns = <300>; 108 }; 109 opp-1300000000 { 110 opp-hz = /bits/ 64 <1300000000>; 111 clock-latency-ns = <300>; 112 }; 113 }; 114 115 psci { 116 compatible = "arm,psci-1.0"; 117 method = "smc"; 118 }; 119 120 clocks { 121 refclk: ref { 122 compatible = "fixed-clock"; 123 #clock-cells = <0>; 124 clock-frequency = <25000000>; 125 }; 126 }; 127 128 emmc_pwrseq: emmc-pwrseq { 129 compatible = "mmc-pwrseq-emmc"; 130 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>; 131 }; 132 133 timer { 134 compatible = "arm,armv8-timer"; 135 interrupts = <1 13 4>, 136 <1 14 4>, 137 <1 11 4>, 138 <1 10 4>; 139 }; 140 141 soc@0 { 142 compatible = "simple-bus"; 143 #address-cells = <1>; 144 #size-cells = <1>; 145 ranges = <0 0 0 0xffffffff>; 146 147 serial0: serial@54006800 { 148 compatible = "socionext,uniphier-uart"; 149 status = "disabled"; 150 reg = <0x54006800 0x40>; 151 interrupts = <0 33 4>; 152 pinctrl-names = "default"; 153 pinctrl-0 = <&pinctrl_uart0>; 154 clocks = <&peri_clk 0>; 155 resets = <&peri_rst 0>; 156 }; 157 158 serial1: serial@54006900 { 159 compatible = "socionext,uniphier-uart"; 160 status = "disabled"; 161 reg = <0x54006900 0x40>; 162 interrupts = <0 35 4>; 163 pinctrl-names = "default"; 164 pinctrl-0 = <&pinctrl_uart1>; 165 clocks = <&peri_clk 1>; 166 resets = <&peri_rst 1>; 167 }; 168 169 serial2: serial@54006a00 { 170 compatible = "socionext,uniphier-uart"; 171 status = "disabled"; 172 reg = <0x54006a00 0x40>; 173 interrupts = <0 37 4>; 174 pinctrl-names = "default"; 175 pinctrl-0 = <&pinctrl_uart2>; 176 clocks = <&peri_clk 2>; 177 resets = <&peri_rst 2>; 178 }; 179 180 serial3: serial@54006b00 { 181 compatible = "socionext,uniphier-uart"; 182 status = "disabled"; 183 reg = <0x54006b00 0x40>; 184 interrupts = <0 177 4>; 185 pinctrl-names = "default"; 186 pinctrl-0 = <&pinctrl_uart3>; 187 clocks = <&peri_clk 3>; 188 resets = <&peri_rst 3>; 189 }; 190 191 gpio: gpio@55000000 { 192 compatible = "socionext,uniphier-gpio"; 193 reg = <0x55000000 0x200>; 194 interrupt-parent = <&aidet>; 195 interrupt-controller; 196 #interrupt-cells = <2>; 197 gpio-controller; 198 #gpio-cells = <2>; 199 gpio-ranges = <&pinctrl 0 0 0>, 200 <&pinctrl 104 0 0>, 201 <&pinctrl 168 0 0>; 202 gpio-ranges-group-names = "gpio_range0", 203 "gpio_range1", 204 "gpio_range2"; 205 ngpios = <286>; 206 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 207 <21 217 3>; 208 }; 209 210 i2c0: i2c@58780000 { 211 compatible = "socionext,uniphier-fi2c"; 212 status = "disabled"; 213 reg = <0x58780000 0x80>; 214 #address-cells = <1>; 215 #size-cells = <0>; 216 interrupts = <0 41 4>; 217 pinctrl-names = "default"; 218 pinctrl-0 = <&pinctrl_i2c0>; 219 clocks = <&peri_clk 4>; 220 resets = <&peri_rst 4>; 221 clock-frequency = <100000>; 222 }; 223 224 i2c1: i2c@58781000 { 225 compatible = "socionext,uniphier-fi2c"; 226 status = "disabled"; 227 reg = <0x58781000 0x80>; 228 #address-cells = <1>; 229 #size-cells = <0>; 230 interrupts = <0 42 4>; 231 pinctrl-names = "default"; 232 pinctrl-0 = <&pinctrl_i2c1>; 233 clocks = <&peri_clk 5>; 234 resets = <&peri_rst 5>; 235 clock-frequency = <100000>; 236 }; 237 238 i2c2: i2c@58782000 { 239 compatible = "socionext,uniphier-fi2c"; 240 status = "disabled"; 241 reg = <0x58782000 0x80>; 242 #address-cells = <1>; 243 #size-cells = <0>; 244 interrupts = <0 43 4>; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&pinctrl_i2c2>; 247 clocks = <&peri_clk 6>; 248 resets = <&peri_rst 6>; 249 clock-frequency = <100000>; 250 }; 251 252 i2c3: i2c@58783000 { 253 compatible = "socionext,uniphier-fi2c"; 254 status = "disabled"; 255 reg = <0x58783000 0x80>; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 interrupts = <0 44 4>; 259 pinctrl-names = "default"; 260 pinctrl-0 = <&pinctrl_i2c3>; 261 clocks = <&peri_clk 7>; 262 resets = <&peri_rst 7>; 263 clock-frequency = <100000>; 264 }; 265 266 /* chip-internal connection for HDMI */ 267 i2c6: i2c@58786000 { 268 compatible = "socionext,uniphier-fi2c"; 269 reg = <0x58786000 0x80>; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 interrupts = <0 26 4>; 273 clocks = <&peri_clk 10>; 274 resets = <&peri_rst 10>; 275 clock-frequency = <400000>; 276 }; 277 278 system_bus: system-bus@58c00000 { 279 compatible = "socionext,uniphier-system-bus"; 280 status = "disabled"; 281 reg = <0x58c00000 0x400>; 282 #address-cells = <2>; 283 #size-cells = <1>; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&pinctrl_system_bus>; 286 }; 287 288 smpctrl@59801000 { 289 compatible = "socionext,uniphier-smpctrl"; 290 reg = <0x59801000 0x400>; 291 }; 292 293 sdctrl@59810000 { 294 compatible = "socionext,uniphier-pxs3-sdctrl", 295 "simple-mfd", "syscon"; 296 reg = <0x59810000 0x400>; 297 298 sd_clk: clock { 299 compatible = "socionext,uniphier-pxs3-sd-clock"; 300 #clock-cells = <1>; 301 }; 302 303 sd_rst: reset { 304 compatible = "socionext,uniphier-pxs3-sd-reset"; 305 #reset-cells = <1>; 306 }; 307 }; 308 309 perictrl@59820000 { 310 compatible = "socionext,uniphier-pxs3-perictrl", 311 "simple-mfd", "syscon"; 312 reg = <0x59820000 0x200>; 313 314 peri_clk: clock { 315 compatible = "socionext,uniphier-pxs3-peri-clock"; 316 #clock-cells = <1>; 317 }; 318 319 peri_rst: reset { 320 compatible = "socionext,uniphier-pxs3-peri-reset"; 321 #reset-cells = <1>; 322 }; 323 }; 324 325 emmc: sdhc@5a000000 { 326 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 327 reg = <0x5a000000 0x400>; 328 interrupts = <0 78 4>; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&pinctrl_emmc>; 331 clocks = <&sys_clk 4>; 332 resets = <&sys_rst 4>; 333 bus-width = <8>; 334 mmc-ddr-1_8v; 335 mmc-hs200-1_8v; 336 mmc-pwrseq = <&emmc_pwrseq>; 337 cdns,phy-input-delay-legacy = <9>; 338 cdns,phy-input-delay-mmc-highspeed = <2>; 339 cdns,phy-input-delay-mmc-ddr = <3>; 340 cdns,phy-dll-delay-sdclk = <21>; 341 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 342 }; 343 344 sd: sdhc@5a400000 { 345 compatible = "socionext,uniphier-sd-v3.1.1"; 346 status = "disabled"; 347 reg = <0x5a400000 0x800>; 348 interrupts = <0 76 4>; 349 pinctrl-names = "default", "uhs"; 350 pinctrl-0 = <&pinctrl_sd>; 351 pinctrl-1 = <&pinctrl_sd_uhs>; 352 clocks = <&sd_clk 0>; 353 reset-names = "host"; 354 resets = <&sd_rst 0>; 355 bus-width = <4>; 356 cap-sd-highspeed; 357 sd-uhs-sdr12; 358 sd-uhs-sdr25; 359 sd-uhs-sdr50; 360 }; 361 362 soc_glue: soc-glue@5f800000 { 363 compatible = "socionext,uniphier-pxs3-soc-glue", 364 "simple-mfd", "syscon"; 365 reg = <0x5f800000 0x2000>; 366 367 pinctrl: pinctrl { 368 compatible = "socionext,uniphier-pxs3-pinctrl"; 369 }; 370 }; 371 372 soc-glue@5f900000 { 373 compatible = "socionext,uniphier-pxs3-soc-glue-debug", 374 "simple-mfd"; 375 #address-cells = <1>; 376 #size-cells = <1>; 377 ranges = <0 0x5f900000 0x2000>; 378 379 efuse@100 { 380 compatible = "socionext,uniphier-efuse"; 381 reg = <0x100 0x28>; 382 }; 383 384 efuse@200 { 385 compatible = "socionext,uniphier-efuse"; 386 reg = <0x200 0x68>; 387 }; 388 }; 389 390 aidet: aidet@5fc20000 { 391 compatible = "socionext,uniphier-pxs3-aidet"; 392 reg = <0x5fc20000 0x200>; 393 interrupt-controller; 394 #interrupt-cells = <2>; 395 }; 396 397 gic: interrupt-controller@5fe00000 { 398 compatible = "arm,gic-v3"; 399 reg = <0x5fe00000 0x10000>, /* GICD */ 400 <0x5fe80000 0x80000>; /* GICR */ 401 interrupt-controller; 402 #interrupt-cells = <3>; 403 interrupts = <1 9 4>; 404 }; 405 406 sysctrl@61840000 { 407 compatible = "socionext,uniphier-pxs3-sysctrl", 408 "simple-mfd", "syscon"; 409 reg = <0x61840000 0x10000>; 410 411 sys_clk: clock { 412 compatible = "socionext,uniphier-pxs3-clock"; 413 #clock-cells = <1>; 414 }; 415 416 sys_rst: reset { 417 compatible = "socionext,uniphier-pxs3-reset"; 418 #reset-cells = <1>; 419 }; 420 421 watchdog { 422 compatible = "socionext,uniphier-wdt"; 423 }; 424 }; 425 426 eth0: ethernet@65000000 { 427 compatible = "socionext,uniphier-pxs3-ave4"; 428 status = "disabled"; 429 reg = <0x65000000 0x8500>; 430 interrupts = <0 66 4>; 431 pinctrl-names = "default"; 432 pinctrl-0 = <&pinctrl_ether_rgmii>; 433 clock-names = "ether"; 434 clocks = <&sys_clk 6>; 435 reset-names = "ether"; 436 resets = <&sys_rst 6>; 437 phy-mode = "rgmii"; 438 local-mac-address = [00 00 00 00 00 00]; 439 socionext,syscon-phy-mode = <&soc_glue 0>; 440 441 mdio0: mdio { 442 #address-cells = <1>; 443 #size-cells = <0>; 444 }; 445 }; 446 447 eth1: ethernet@65200000 { 448 compatible = "socionext,uniphier-pxs3-ave4"; 449 status = "disabled"; 450 reg = <0x65200000 0x8500>; 451 interrupts = <0 67 4>; 452 pinctrl-names = "default"; 453 pinctrl-0 = <&pinctrl_ether1_rgmii>; 454 clock-names = "ether"; 455 clocks = <&sys_clk 7>; 456 reset-names = "ether"; 457 resets = <&sys_rst 7>; 458 phy-mode = "rgmii"; 459 local-mac-address = [00 00 00 00 00 00]; 460 socionext,syscon-phy-mode = <&soc_glue 1>; 461 462 mdio1: mdio { 463 #address-cells = <1>; 464 #size-cells = <0>; 465 }; 466 }; 467 468 usb0: usb@65b00000 { 469 compatible = "socionext,uniphier-pxs3-dwc3"; 470 status = "disabled"; 471 reg = <0x65b00000 0x1000>; 472 #address-cells = <1>; 473 #size-cells = <1>; 474 ranges; 475 pinctrl-names = "default"; 476 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; 477 dwc3@65a00000 { 478 compatible = "snps,dwc3"; 479 reg = <0x65a00000 0x10000>; 480 interrupts = <0 134 4>; 481 dr_mode = "host"; 482 tx-fifo-resize; 483 }; 484 }; 485 486 usb1: usb@65d00000 { 487 compatible = "socionext,uniphier-pxs3-dwc3"; 488 status = "disabled"; 489 reg = <0x65d00000 0x1000>; 490 #address-cells = <1>; 491 #size-cells = <1>; 492 ranges; 493 pinctrl-names = "default"; 494 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; 495 dwc3@65c00000 { 496 compatible = "snps,dwc3"; 497 reg = <0x65c00000 0x10000>; 498 interrupts = <0 137 4>; 499 dr_mode = "host"; 500 tx-fifo-resize; 501 }; 502 }; 503 504 nand: nand@68000000 { 505 compatible = "socionext,uniphier-denali-nand-v5b"; 506 status = "disabled"; 507 reg-names = "nand_data", "denali_reg"; 508 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 509 interrupts = <0 65 4>; 510 pinctrl-names = "default"; 511 pinctrl-0 = <&pinctrl_nand>; 512 clocks = <&sys_clk 2>; 513 resets = <&sys_rst 2>; 514 }; 515 }; 516}; 517 518#include "uniphier-pinctrl.dtsi" 519