1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Device Tree Source for UniPhier PXs3 SoC 4// 5// Copyright (C) 2017 Socionext Inc. 6// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/gpio/uniphier-gpio.h> 10 11/memreserve/ 0x80000000 0x02000000; 12 13/ { 14 compatible = "socionext,uniphier-pxs3"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 interrupt-parent = <&gic>; 18 19 cpus { 20 #address-cells = <2>; 21 #size-cells = <0>; 22 23 cpu-map { 24 cluster0 { 25 core0 { 26 cpu = <&cpu0>; 27 }; 28 core1 { 29 cpu = <&cpu1>; 30 }; 31 core2 { 32 cpu = <&cpu2>; 33 }; 34 core3 { 35 cpu = <&cpu3>; 36 }; 37 }; 38 }; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53", "arm,armv8"; 43 reg = <0 0x000>; 44 clocks = <&sys_clk 33>; 45 enable-method = "psci"; 46 operating-points-v2 = <&cluster0_opp>; 47 }; 48 49 cpu1: cpu@1 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53", "arm,armv8"; 52 reg = <0 0x001>; 53 clocks = <&sys_clk 33>; 54 enable-method = "psci"; 55 operating-points-v2 = <&cluster0_opp>; 56 }; 57 58 cpu2: cpu@2 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a53", "arm,armv8"; 61 reg = <0 0x002>; 62 clocks = <&sys_clk 33>; 63 enable-method = "psci"; 64 operating-points-v2 = <&cluster0_opp>; 65 }; 66 67 cpu3: cpu@3 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a53", "arm,armv8"; 70 reg = <0 0x003>; 71 clocks = <&sys_clk 33>; 72 enable-method = "psci"; 73 operating-points-v2 = <&cluster0_opp>; 74 }; 75 }; 76 77 cluster0_opp: opp-table { 78 compatible = "operating-points-v2"; 79 opp-shared; 80 81 opp-250000000 { 82 opp-hz = /bits/ 64 <250000000>; 83 clock-latency-ns = <300>; 84 }; 85 opp-325000000 { 86 opp-hz = /bits/ 64 <325000000>; 87 clock-latency-ns = <300>; 88 }; 89 opp-500000000 { 90 opp-hz = /bits/ 64 <500000000>; 91 clock-latency-ns = <300>; 92 }; 93 opp-650000000 { 94 opp-hz = /bits/ 64 <650000000>; 95 clock-latency-ns = <300>; 96 }; 97 opp-666667000 { 98 opp-hz = /bits/ 64 <666667000>; 99 clock-latency-ns = <300>; 100 }; 101 opp-866667000 { 102 opp-hz = /bits/ 64 <866667000>; 103 clock-latency-ns = <300>; 104 }; 105 opp-1000000000 { 106 opp-hz = /bits/ 64 <1000000000>; 107 clock-latency-ns = <300>; 108 }; 109 opp-1300000000 { 110 opp-hz = /bits/ 64 <1300000000>; 111 clock-latency-ns = <300>; 112 }; 113 }; 114 115 psci { 116 compatible = "arm,psci-1.0"; 117 method = "smc"; 118 }; 119 120 clocks { 121 refclk: ref { 122 compatible = "fixed-clock"; 123 #clock-cells = <0>; 124 clock-frequency = <25000000>; 125 }; 126 }; 127 128 emmc_pwrseq: emmc-pwrseq { 129 compatible = "mmc-pwrseq-emmc"; 130 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>; 131 }; 132 133 timer { 134 compatible = "arm,armv8-timer"; 135 interrupts = <1 13 4>, 136 <1 14 4>, 137 <1 11 4>, 138 <1 10 4>; 139 }; 140 141 soc@0 { 142 compatible = "simple-bus"; 143 #address-cells = <1>; 144 #size-cells = <1>; 145 ranges = <0 0 0 0xffffffff>; 146 147 serial0: serial@54006800 { 148 compatible = "socionext,uniphier-uart"; 149 status = "disabled"; 150 reg = <0x54006800 0x40>; 151 interrupts = <0 33 4>; 152 pinctrl-names = "default"; 153 pinctrl-0 = <&pinctrl_uart0>; 154 clocks = <&peri_clk 0>; 155 clock-frequency = <58820000>; 156 resets = <&peri_rst 0>; 157 }; 158 159 serial1: serial@54006900 { 160 compatible = "socionext,uniphier-uart"; 161 status = "disabled"; 162 reg = <0x54006900 0x40>; 163 interrupts = <0 35 4>; 164 pinctrl-names = "default"; 165 pinctrl-0 = <&pinctrl_uart1>; 166 clocks = <&peri_clk 1>; 167 clock-frequency = <58820000>; 168 resets = <&peri_rst 1>; 169 }; 170 171 serial2: serial@54006a00 { 172 compatible = "socionext,uniphier-uart"; 173 status = "disabled"; 174 reg = <0x54006a00 0x40>; 175 interrupts = <0 37 4>; 176 pinctrl-names = "default"; 177 pinctrl-0 = <&pinctrl_uart2>; 178 clocks = <&peri_clk 2>; 179 clock-frequency = <58820000>; 180 resets = <&peri_rst 2>; 181 }; 182 183 serial3: serial@54006b00 { 184 compatible = "socionext,uniphier-uart"; 185 status = "disabled"; 186 reg = <0x54006b00 0x40>; 187 interrupts = <0 177 4>; 188 pinctrl-names = "default"; 189 pinctrl-0 = <&pinctrl_uart3>; 190 clocks = <&peri_clk 3>; 191 clock-frequency = <58820000>; 192 resets = <&peri_rst 3>; 193 }; 194 195 gpio: gpio@55000000 { 196 compatible = "socionext,uniphier-gpio"; 197 reg = <0x55000000 0x200>; 198 interrupt-parent = <&aidet>; 199 interrupt-controller; 200 #interrupt-cells = <2>; 201 gpio-controller; 202 #gpio-cells = <2>; 203 gpio-ranges = <&pinctrl 0 0 0>, 204 <&pinctrl 104 0 0>, 205 <&pinctrl 168 0 0>; 206 gpio-ranges-group-names = "gpio_range0", 207 "gpio_range1", 208 "gpio_range2"; 209 ngpios = <286>; 210 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 211 <21 217 3>; 212 }; 213 214 i2c0: i2c@58780000 { 215 compatible = "socionext,uniphier-fi2c"; 216 status = "disabled"; 217 reg = <0x58780000 0x80>; 218 #address-cells = <1>; 219 #size-cells = <0>; 220 interrupts = <0 41 4>; 221 pinctrl-names = "default"; 222 pinctrl-0 = <&pinctrl_i2c0>; 223 clocks = <&peri_clk 4>; 224 resets = <&peri_rst 4>; 225 clock-frequency = <100000>; 226 }; 227 228 i2c1: i2c@58781000 { 229 compatible = "socionext,uniphier-fi2c"; 230 status = "disabled"; 231 reg = <0x58781000 0x80>; 232 #address-cells = <1>; 233 #size-cells = <0>; 234 interrupts = <0 42 4>; 235 pinctrl-names = "default"; 236 pinctrl-0 = <&pinctrl_i2c1>; 237 clocks = <&peri_clk 5>; 238 resets = <&peri_rst 5>; 239 clock-frequency = <100000>; 240 }; 241 242 i2c2: i2c@58782000 { 243 compatible = "socionext,uniphier-fi2c"; 244 status = "disabled"; 245 reg = <0x58782000 0x80>; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 interrupts = <0 43 4>; 249 pinctrl-names = "default"; 250 pinctrl-0 = <&pinctrl_i2c2>; 251 clocks = <&peri_clk 6>; 252 resets = <&peri_rst 6>; 253 clock-frequency = <100000>; 254 }; 255 256 i2c3: i2c@58783000 { 257 compatible = "socionext,uniphier-fi2c"; 258 status = "disabled"; 259 reg = <0x58783000 0x80>; 260 #address-cells = <1>; 261 #size-cells = <0>; 262 interrupts = <0 44 4>; 263 pinctrl-names = "default"; 264 pinctrl-0 = <&pinctrl_i2c3>; 265 clocks = <&peri_clk 7>; 266 resets = <&peri_rst 7>; 267 clock-frequency = <100000>; 268 }; 269 270 /* chip-internal connection for HDMI */ 271 i2c6: i2c@58786000 { 272 compatible = "socionext,uniphier-fi2c"; 273 reg = <0x58786000 0x80>; 274 #address-cells = <1>; 275 #size-cells = <0>; 276 interrupts = <0 26 4>; 277 clocks = <&peri_clk 10>; 278 resets = <&peri_rst 10>; 279 clock-frequency = <400000>; 280 }; 281 282 system_bus: system-bus@58c00000 { 283 compatible = "socionext,uniphier-system-bus"; 284 status = "disabled"; 285 reg = <0x58c00000 0x400>; 286 #address-cells = <2>; 287 #size-cells = <1>; 288 pinctrl-names = "default"; 289 pinctrl-0 = <&pinctrl_system_bus>; 290 }; 291 292 smpctrl@59801000 { 293 compatible = "socionext,uniphier-smpctrl"; 294 reg = <0x59801000 0x400>; 295 }; 296 297 sdctrl@59810000 { 298 compatible = "socionext,uniphier-pxs3-sdctrl", 299 "simple-mfd", "syscon"; 300 reg = <0x59810000 0x400>; 301 302 sd_clk: clock { 303 compatible = "socionext,uniphier-pxs3-sd-clock"; 304 #clock-cells = <1>; 305 }; 306 307 sd_rst: reset { 308 compatible = "socionext,uniphier-pxs3-sd-reset"; 309 #reset-cells = <1>; 310 }; 311 }; 312 313 perictrl@59820000 { 314 compatible = "socionext,uniphier-pxs3-perictrl", 315 "simple-mfd", "syscon"; 316 reg = <0x59820000 0x200>; 317 318 peri_clk: clock { 319 compatible = "socionext,uniphier-pxs3-peri-clock"; 320 #clock-cells = <1>; 321 }; 322 323 peri_rst: reset { 324 compatible = "socionext,uniphier-pxs3-peri-reset"; 325 #reset-cells = <1>; 326 }; 327 }; 328 329 emmc: sdhc@5a000000 { 330 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 331 reg = <0x5a000000 0x400>; 332 interrupts = <0 78 4>; 333 pinctrl-names = "default"; 334 pinctrl-0 = <&pinctrl_emmc_1v8>; 335 clocks = <&sys_clk 4>; 336 resets = <&sys_rst 4>; 337 bus-width = <8>; 338 mmc-ddr-1_8v; 339 mmc-hs200-1_8v; 340 mmc-pwrseq = <&emmc_pwrseq>; 341 cdns,phy-input-delay-legacy = <9>; 342 cdns,phy-input-delay-mmc-highspeed = <2>; 343 cdns,phy-input-delay-mmc-ddr = <3>; 344 cdns,phy-dll-delay-sdclk = <21>; 345 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 346 }; 347 348 sd: sdhc@5a400000 { 349 compatible = "socionext,uniphier-sdhc"; 350 status = "disabled"; 351 reg = <0x5a400000 0x800>; 352 interrupts = <0 76 4>; 353 pinctrl-names = "default"; 354 pinctrl-0 = <&pinctrl_sd>; 355 clocks = <&sd_clk 0>; 356 reset-names = "host"; 357 resets = <&sd_rst 0>; 358 bus-width = <4>; 359 cap-sd-highspeed; 360 }; 361 362 soc_glue: soc-glue@5f800000 { 363 compatible = "socionext,uniphier-pxs3-soc-glue", 364 "simple-mfd", "syscon"; 365 reg = <0x5f800000 0x2000>; 366 367 pinctrl: pinctrl { 368 compatible = "socionext,uniphier-pxs3-pinctrl"; 369 }; 370 }; 371 372 soc-glue@5f900000 { 373 compatible = "socionext,uniphier-pxs3-soc-glue-debug", 374 "simple-mfd"; 375 #address-cells = <1>; 376 #size-cells = <1>; 377 ranges = <0 0x5f900000 0x2000>; 378 379 efuse@100 { 380 compatible = "socionext,uniphier-efuse"; 381 reg = <0x100 0x28>; 382 }; 383 384 efuse@200 { 385 compatible = "socionext,uniphier-efuse"; 386 reg = <0x200 0x68>; 387 }; 388 }; 389 390 aidet: aidet@5fc20000 { 391 compatible = "socionext,uniphier-pxs3-aidet"; 392 reg = <0x5fc20000 0x200>; 393 interrupt-controller; 394 #interrupt-cells = <2>; 395 }; 396 397 gic: interrupt-controller@5fe00000 { 398 compatible = "arm,gic-v3"; 399 reg = <0x5fe00000 0x10000>, /* GICD */ 400 <0x5fe80000 0x80000>; /* GICR */ 401 interrupt-controller; 402 #interrupt-cells = <3>; 403 interrupts = <1 9 4>; 404 }; 405 406 sysctrl@61840000 { 407 compatible = "socionext,uniphier-pxs3-sysctrl", 408 "simple-mfd", "syscon"; 409 reg = <0x61840000 0x10000>; 410 411 sys_clk: clock { 412 compatible = "socionext,uniphier-pxs3-clock"; 413 #clock-cells = <1>; 414 }; 415 416 sys_rst: reset { 417 compatible = "socionext,uniphier-pxs3-reset"; 418 #reset-cells = <1>; 419 }; 420 421 watchdog { 422 compatible = "socionext,uniphier-wdt"; 423 }; 424 }; 425 426 eth0: ethernet@65000000 { 427 compatible = "socionext,uniphier-pxs3-ave4"; 428 status = "disabled"; 429 reg = <0x65000000 0x8500>; 430 interrupts = <0 66 4>; 431 pinctrl-names = "default"; 432 pinctrl-0 = <&pinctrl_ether_rgmii>; 433 clock-names = "ether"; 434 clocks = <&sys_clk 6>; 435 reset-names = "ether"; 436 resets = <&sys_rst 6>; 437 phy-mode = "rgmii"; 438 local-mac-address = [00 00 00 00 00 00]; 439 socionext,syscon-phy-mode = <&soc_glue 0>; 440 441 mdio0: mdio { 442 #address-cells = <1>; 443 #size-cells = <0>; 444 }; 445 }; 446 447 eth1: ethernet@65200000 { 448 compatible = "socionext,uniphier-pxs3-ave4"; 449 status = "disabled"; 450 reg = <0x65200000 0x8500>; 451 interrupts = <0 67 4>; 452 pinctrl-names = "default"; 453 pinctrl-0 = <&pinctrl_ether1_rgmii>; 454 clock-names = "ether"; 455 clocks = <&sys_clk 7>; 456 reset-names = "ether"; 457 resets = <&sys_rst 7>; 458 phy-mode = "rgmii"; 459 local-mac-address = [00 00 00 00 00 00]; 460 socionext,syscon-phy-mode = <&soc_glue 1>; 461 462 mdio1: mdio { 463 #address-cells = <1>; 464 #size-cells = <0>; 465 }; 466 }; 467 468 usb0: usb@65b00000 { 469 compatible = "socionext,uniphier-pxs3-dwc3"; 470 status = "disabled"; 471 reg = <0x65b00000 0x1000>; 472 #address-cells = <1>; 473 #size-cells = <1>; 474 ranges; 475 pinctrl-names = "default"; 476 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; 477 dwc3@65a00000 { 478 compatible = "snps,dwc3"; 479 reg = <0x65a00000 0x10000>; 480 interrupts = <0 134 4>; 481 dr_mode = "host"; 482 tx-fifo-resize; 483 }; 484 }; 485 486 usb1: usb@65d00000 { 487 compatible = "socionext,uniphier-pxs3-dwc3"; 488 status = "disabled"; 489 reg = <0x65d00000 0x1000>; 490 #address-cells = <1>; 491 #size-cells = <1>; 492 ranges; 493 pinctrl-names = "default"; 494 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; 495 dwc3@65c00000 { 496 compatible = "snps,dwc3"; 497 reg = <0x65c00000 0x10000>; 498 interrupts = <0 137 4>; 499 dr_mode = "host"; 500 tx-fifo-resize; 501 }; 502 }; 503 504 nand: nand@68000000 { 505 compatible = "socionext,uniphier-denali-nand-v5b"; 506 status = "disabled"; 507 reg-names = "nand_data", "denali_reg"; 508 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 509 interrupts = <0 65 4>; 510 pinctrl-names = "default"; 511 pinctrl-0 = <&pinctrl_nand>; 512 clocks = <&sys_clk 2>; 513 resets = <&sys_rst 2>; 514 }; 515 }; 516}; 517 518#include "uniphier-pinctrl.dtsi" 519