1/* 2 * Device Tree Source for UniPhier PXs3 SoC 3 * 4 * Copyright (C) 2017 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * This file is dual-licensed: you can use it either under the terms 8 * of the GPL or the X11 license, at your option. Note that this dual 9 * licensing only applies to this file, and not this project as a 10 * whole. 11 * 12 * a) This file is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of the 15 * License, or (at your option) any later version. 16 * 17 * This file is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * Or, alternatively, 23 * 24 * b) Permission is hereby granted, free of charge, to any person 25 * obtaining a copy of this software and associated documentation 26 * files (the "Software"), to deal in the Software without 27 * restriction, including without limitation the rights to use, 28 * copy, modify, merge, publish, distribute, sublicense, and/or 29 * sell copies of the Software, and to permit persons to whom the 30 * Software is furnished to do so, subject to the following 31 * conditions: 32 * 33 * The above copyright notice and this permission notice shall be 34 * included in all copies or substantial portions of the Software. 35 * 36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 43 * OTHER DEALINGS IN THE SOFTWARE. 44 */ 45 46/memreserve/ 0x80000000 0x00080000; 47 48/ { 49 compatible = "socionext,uniphier-pxs3"; 50 #address-cells = <2>; 51 #size-cells = <2>; 52 interrupt-parent = <&gic>; 53 54 cpus { 55 #address-cells = <2>; 56 #size-cells = <0>; 57 58 cpu-map { 59 cluster0 { 60 core0 { 61 cpu = <&cpu0>; 62 }; 63 core1 { 64 cpu = <&cpu1>; 65 }; 66 core2 { 67 cpu = <&cpu2>; 68 }; 69 core3 { 70 cpu = <&cpu3>; 71 }; 72 }; 73 }; 74 75 cpu0: cpu@0 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a53", "arm,armv8"; 78 reg = <0 0x000>; 79 enable-method = "psci"; 80 }; 81 82 cpu1: cpu@1 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a53", "arm,armv8"; 85 reg = <0 0x001>; 86 enable-method = "psci"; 87 }; 88 89 cpu2: cpu@2 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a53", "arm,armv8"; 92 reg = <0 0x002>; 93 enable-method = "psci"; 94 }; 95 96 cpu3: cpu@3 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a53", "arm,armv8"; 99 reg = <0 0x003>; 100 enable-method = "psci"; 101 }; 102 }; 103 104 psci { 105 compatible = "arm,psci-1.0"; 106 method = "smc"; 107 }; 108 109 clocks { 110 refclk: ref { 111 compatible = "fixed-clock"; 112 #clock-cells = <0>; 113 clock-frequency = <25000000>; 114 }; 115 }; 116 117 timer { 118 compatible = "arm,armv8-timer"; 119 interrupts = <1 13 4>, 120 <1 14 4>, 121 <1 11 4>, 122 <1 10 4>; 123 }; 124 125 soc@0 { 126 compatible = "simple-bus"; 127 #address-cells = <1>; 128 #size-cells = <1>; 129 ranges = <0 0 0 0xffffffff>; 130 131 serial0: serial@54006800 { 132 compatible = "socionext,uniphier-uart"; 133 status = "disabled"; 134 reg = <0x54006800 0x40>; 135 interrupts = <0 33 4>; 136 pinctrl-names = "default"; 137 pinctrl-0 = <&pinctrl_uart0>; 138 clocks = <&peri_clk 0>; 139 clock-frequency = <58820000>; 140 }; 141 142 serial1: serial@54006900 { 143 compatible = "socionext,uniphier-uart"; 144 status = "disabled"; 145 reg = <0x54006900 0x40>; 146 interrupts = <0 35 4>; 147 pinctrl-names = "default"; 148 pinctrl-0 = <&pinctrl_uart1>; 149 clocks = <&peri_clk 1>; 150 clock-frequency = <58820000>; 151 }; 152 153 serial2: serial@54006a00 { 154 compatible = "socionext,uniphier-uart"; 155 status = "disabled"; 156 reg = <0x54006a00 0x40>; 157 interrupts = <0 37 4>; 158 pinctrl-names = "default"; 159 pinctrl-0 = <&pinctrl_uart2>; 160 clocks = <&peri_clk 2>; 161 clock-frequency = <58820000>; 162 }; 163 164 serial3: serial@54006b00 { 165 compatible = "socionext,uniphier-uart"; 166 status = "disabled"; 167 reg = <0x54006b00 0x40>; 168 interrupts = <0 177 4>; 169 pinctrl-names = "default"; 170 pinctrl-0 = <&pinctrl_uart3>; 171 clocks = <&peri_clk 3>; 172 clock-frequency = <58820000>; 173 }; 174 175 i2c0: i2c@58780000 { 176 compatible = "socionext,uniphier-fi2c"; 177 status = "disabled"; 178 reg = <0x58780000 0x80>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 interrupts = <0 41 4>; 182 pinctrl-names = "default"; 183 pinctrl-0 = <&pinctrl_i2c0>; 184 clocks = <&peri_clk 4>; 185 clock-frequency = <100000>; 186 }; 187 188 i2c1: i2c@58781000 { 189 compatible = "socionext,uniphier-fi2c"; 190 status = "disabled"; 191 reg = <0x58781000 0x80>; 192 #address-cells = <1>; 193 #size-cells = <0>; 194 interrupts = <0 42 4>; 195 pinctrl-names = "default"; 196 pinctrl-0 = <&pinctrl_i2c1>; 197 clocks = <&peri_clk 5>; 198 clock-frequency = <100000>; 199 }; 200 201 i2c2: i2c@58782000 { 202 compatible = "socionext,uniphier-fi2c"; 203 status = "disabled"; 204 reg = <0x58782000 0x80>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 interrupts = <0 43 4>; 208 clocks = <&peri_clk 6>; 209 clock-frequency = <100000>; 210 }; 211 212 i2c3: i2c@58783000 { 213 compatible = "socionext,uniphier-fi2c"; 214 status = "disabled"; 215 reg = <0x58783000 0x80>; 216 #address-cells = <1>; 217 #size-cells = <0>; 218 interrupts = <0 44 4>; 219 pinctrl-names = "default"; 220 pinctrl-0 = <&pinctrl_i2c3>; 221 clocks = <&peri_clk 7>; 222 clock-frequency = <100000>; 223 }; 224 225 /* chip-internal connection for HDMI */ 226 i2c6: i2c@58786000 { 227 compatible = "socionext,uniphier-fi2c"; 228 reg = <0x58786000 0x80>; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 interrupts = <0 26 4>; 232 clocks = <&peri_clk 10>; 233 clock-frequency = <400000>; 234 }; 235 236 system_bus: system-bus@58c00000 { 237 compatible = "socionext,uniphier-system-bus"; 238 status = "disabled"; 239 reg = <0x58c00000 0x400>; 240 #address-cells = <2>; 241 #size-cells = <1>; 242 pinctrl-names = "default"; 243 pinctrl-0 = <&pinctrl_system_bus>; 244 }; 245 246 smpctrl@59801000 { 247 compatible = "socionext,uniphier-smpctrl"; 248 reg = <0x59801000 0x400>; 249 }; 250 251 sdctrl@59810000 { 252 compatible = "socionext,uniphier-pxs3-sdctrl", 253 "simple-mfd", "syscon"; 254 reg = <0x59810000 0x800>; 255 256 sd_clk: clock { 257 compatible = "socionext,uniphier-pxs3-sd-clock"; 258 #clock-cells = <1>; 259 }; 260 261 sd_rst: reset { 262 compatible = "socionext,uniphier-pxs3-sd-reset"; 263 #reset-cells = <1>; 264 }; 265 }; 266 267 perictrl@59820000 { 268 compatible = "socionext,uniphier-pxs3-perictrl", 269 "simple-mfd", "syscon"; 270 reg = <0x59820000 0x200>; 271 272 peri_clk: clock { 273 compatible = "socionext,uniphier-pxs3-peri-clock"; 274 #clock-cells = <1>; 275 }; 276 277 peri_rst: reset { 278 compatible = "socionext,uniphier-pxs3-peri-reset"; 279 #reset-cells = <1>; 280 }; 281 }; 282 283 emmc: sdhc@5a000000 { 284 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 285 status = "disabled"; 286 reg = <0x5a000000 0x400>; 287 interrupts = <0 78 4>; 288 pinctrl-names = "default"; 289 pinctrl-0 = <&pinctrl_emmc_1v8>; 290 clocks = <&sys_clk 4>; 291 bus-width = <8>; 292 mmc-ddr-1_8v; 293 mmc-hs200-1_8v; 294 }; 295 296 sd: sdhc@5a400000 { 297 compatible = "socionext,uniphier-sdhc"; 298 status = "disabled"; 299 reg = <0x5a400000 0x800>; 300 interrupts = <0 76 4>; 301 pinctrl-names = "default"; 302 pinctrl-0 = <&pinctrl_sd>; 303 clocks = <&sd_clk 0>; 304 reset-names = "host"; 305 resets = <&sd_rst 0>; 306 bus-width = <4>; 307 cap-sd-highspeed; 308 }; 309 310 soc-glue@5f800000 { 311 compatible = "socionext,uniphier-pxs3-soc-glue", 312 "simple-mfd", "syscon"; 313 reg = <0x5f800000 0x2000>; 314 315 pinctrl: pinctrl { 316 compatible = "socionext,uniphier-pxs3-pinctrl"; 317 }; 318 }; 319 320 aidet@5fc20000 { 321 compatible = "simple-mfd", "syscon"; 322 reg = <0x5fc20000 0x200>; 323 }; 324 325 gic: interrupt-controller@5fe00000 { 326 compatible = "arm,gic-v3"; 327 reg = <0x5fe00000 0x10000>, /* GICD */ 328 <0x5fe80000 0x80000>; /* GICR */ 329 interrupt-controller; 330 #interrupt-cells = <3>; 331 interrupts = <1 9 4>; 332 }; 333 334 sysctrl@61840000 { 335 compatible = "socionext,uniphier-pxs3-sysctrl", 336 "simple-mfd", "syscon"; 337 reg = <0x61840000 0x10000>; 338 339 sys_clk: clock { 340 compatible = "socionext,uniphier-pxs3-clock"; 341 #clock-cells = <1>; 342 }; 343 344 sys_rst: reset { 345 compatible = "socionext,uniphier-pxs3-reset"; 346 #reset-cells = <1>; 347 }; 348 }; 349 350 nand: nand@68000000 { 351 compatible = "socionext,denali-nand-v5b"; 352 status = "disabled"; 353 reg-names = "nand_data", "denali_reg"; 354 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 355 interrupts = <0 65 4>; 356 pinctrl-names = "default"; 357 pinctrl-0 = <&pinctrl_nand>; 358 clocks = <&sys_clk 2>; 359 nand-ecc-strength = <8>; 360 }; 361 }; 362}; 363 364/include/ "uniphier-pinctrl.dtsi" 365