1/* 2 * Device Tree Source for UniPhier PXs2 SoC 3 * 4 * Copyright (C) 2015-2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ X11 8 */ 9 10/include/ "skeleton.dtsi" 11 12/ { 13 compatible = "socionext,uniphier-pxs2"; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu@0 { 20 device_type = "cpu"; 21 compatible = "arm,cortex-a9"; 22 reg = <0>; 23 clocks = <&sys_clk 32>; 24 enable-method = "psci"; 25 next-level-cache = <&l2>; 26 operating-points-v2 = <&cpu_opp>; 27 }; 28 29 cpu@1 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a9"; 32 reg = <1>; 33 clocks = <&sys_clk 32>; 34 enable-method = "psci"; 35 next-level-cache = <&l2>; 36 operating-points-v2 = <&cpu_opp>; 37 }; 38 39 cpu@2 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a9"; 42 reg = <2>; 43 clocks = <&sys_clk 32>; 44 enable-method = "psci"; 45 next-level-cache = <&l2>; 46 operating-points-v2 = <&cpu_opp>; 47 }; 48 49 cpu@3 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a9"; 52 reg = <3>; 53 clocks = <&sys_clk 32>; 54 enable-method = "psci"; 55 next-level-cache = <&l2>; 56 operating-points-v2 = <&cpu_opp>; 57 }; 58 }; 59 60 cpu_opp: opp_table { 61 compatible = "operating-points-v2"; 62 opp-shared; 63 64 opp@100000000 { 65 opp-hz = /bits/ 64 <100000000>; 66 clock-latency-ns = <300>; 67 }; 68 opp@150000000 { 69 opp-hz = /bits/ 64 <150000000>; 70 clock-latency-ns = <300>; 71 }; 72 opp@200000000 { 73 opp-hz = /bits/ 64 <200000000>; 74 clock-latency-ns = <300>; 75 }; 76 opp@300000000 { 77 opp-hz = /bits/ 64 <300000000>; 78 clock-latency-ns = <300>; 79 }; 80 opp@400000000 { 81 opp-hz = /bits/ 64 <400000000>; 82 clock-latency-ns = <300>; 83 }; 84 opp@600000000 { 85 opp-hz = /bits/ 64 <600000000>; 86 clock-latency-ns = <300>; 87 }; 88 opp@800000000 { 89 opp-hz = /bits/ 64 <800000000>; 90 clock-latency-ns = <300>; 91 }; 92 opp@1200000000 { 93 opp-hz = /bits/ 64 <1200000000>; 94 clock-latency-ns = <300>; 95 }; 96 }; 97 98 psci { 99 compatible = "arm,psci-0.2"; 100 method = "smc"; 101 }; 102 103 clocks { 104 refclk: ref { 105 compatible = "fixed-clock"; 106 #clock-cells = <0>; 107 clock-frequency = <25000000>; 108 }; 109 110 arm_timer_clk: arm_timer_clk { 111 #clock-cells = <0>; 112 compatible = "fixed-clock"; 113 clock-frequency = <50000000>; 114 }; 115 116 i2c_clk: i2c_clk { 117 #clock-cells = <0>; 118 compatible = "fixed-clock"; 119 clock-frequency = <50000000>; 120 }; 121 }; 122 123 soc { 124 compatible = "simple-bus"; 125 #address-cells = <1>; 126 #size-cells = <1>; 127 ranges; 128 interrupt-parent = <&intc>; 129 u-boot,dm-pre-reloc; 130 131 l2: l2-cache@500c0000 { 132 compatible = "socionext,uniphier-system-cache"; 133 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, 134 <0x506c0000 0x400>; 135 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; 136 cache-unified; 137 cache-size = <(1280 * 1024)>; 138 cache-sets = <512>; 139 cache-line-size = <128>; 140 cache-level = <2>; 141 }; 142 143 serial0: serial@54006800 { 144 compatible = "socionext,uniphier-uart"; 145 status = "disabled"; 146 reg = <0x54006800 0x40>; 147 interrupts = <0 33 4>; 148 pinctrl-names = "default"; 149 pinctrl-0 = <&pinctrl_uart0>; 150 clocks = <&peri_clk 0>; 151 clock-frequency = <88900000>; 152 }; 153 154 serial1: serial@54006900 { 155 compatible = "socionext,uniphier-uart"; 156 status = "disabled"; 157 reg = <0x54006900 0x40>; 158 interrupts = <0 35 4>; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&pinctrl_uart1>; 161 clocks = <&peri_clk 1>; 162 clock-frequency = <88900000>; 163 }; 164 165 serial2: serial@54006a00 { 166 compatible = "socionext,uniphier-uart"; 167 status = "disabled"; 168 reg = <0x54006a00 0x40>; 169 interrupts = <0 37 4>; 170 pinctrl-names = "default"; 171 pinctrl-0 = <&pinctrl_uart2>; 172 clocks = <&peri_clk 2>; 173 clock-frequency = <88900000>; 174 }; 175 176 serial3: serial@54006b00 { 177 compatible = "socionext,uniphier-uart"; 178 status = "disabled"; 179 reg = <0x54006b00 0x40>; 180 interrupts = <0 177 4>; 181 pinctrl-names = "default"; 182 pinctrl-0 = <&pinctrl_uart3>; 183 clocks = <&peri_clk 3>; 184 clock-frequency = <88900000>; 185 }; 186 187 port0x: gpio@55000008 { 188 compatible = "socionext,uniphier-gpio"; 189 reg = <0x55000008 0x8>; 190 gpio-controller; 191 #gpio-cells = <2>; 192 }; 193 194 port1x: gpio@55000010 { 195 compatible = "socionext,uniphier-gpio"; 196 reg = <0x55000010 0x8>; 197 gpio-controller; 198 #gpio-cells = <2>; 199 }; 200 201 port2x: gpio@55000018 { 202 compatible = "socionext,uniphier-gpio"; 203 reg = <0x55000018 0x8>; 204 gpio-controller; 205 #gpio-cells = <2>; 206 }; 207 208 port3x: gpio@55000020 { 209 compatible = "socionext,uniphier-gpio"; 210 reg = <0x55000020 0x8>; 211 gpio-controller; 212 #gpio-cells = <2>; 213 }; 214 215 port4: gpio@55000028 { 216 compatible = "socionext,uniphier-gpio"; 217 reg = <0x55000028 0x8>; 218 gpio-controller; 219 #gpio-cells = <2>; 220 }; 221 222 port5x: gpio@55000030 { 223 compatible = "socionext,uniphier-gpio"; 224 reg = <0x55000030 0x8>; 225 gpio-controller; 226 #gpio-cells = <2>; 227 }; 228 229 port6x: gpio@55000038 { 230 compatible = "socionext,uniphier-gpio"; 231 reg = <0x55000038 0x8>; 232 gpio-controller; 233 #gpio-cells = <2>; 234 }; 235 236 port7x: gpio@55000040 { 237 compatible = "socionext,uniphier-gpio"; 238 reg = <0x55000040 0x8>; 239 gpio-controller; 240 #gpio-cells = <2>; 241 }; 242 243 port8x: gpio@55000048 { 244 compatible = "socionext,uniphier-gpio"; 245 reg = <0x55000048 0x8>; 246 gpio-controller; 247 #gpio-cells = <2>; 248 }; 249 250 port9x: gpio@55000050 { 251 compatible = "socionext,uniphier-gpio"; 252 reg = <0x55000050 0x8>; 253 gpio-controller; 254 #gpio-cells = <2>; 255 }; 256 257 port10x: gpio@55000058 { 258 compatible = "socionext,uniphier-gpio"; 259 reg = <0x55000058 0x8>; 260 gpio-controller; 261 #gpio-cells = <2>; 262 }; 263 264 port12x: gpio@55000068 { 265 compatible = "socionext,uniphier-gpio"; 266 reg = <0x55000068 0x8>; 267 gpio-controller; 268 #gpio-cells = <2>; 269 }; 270 271 port13x: gpio@55000070 { 272 compatible = "socionext,uniphier-gpio"; 273 reg = <0x55000070 0x8>; 274 gpio-controller; 275 #gpio-cells = <2>; 276 }; 277 278 port14x: gpio@55000078 { 279 compatible = "socionext,uniphier-gpio"; 280 reg = <0x55000078 0x8>; 281 gpio-controller; 282 #gpio-cells = <2>; 283 }; 284 285 port15x: gpio@55000080 { 286 compatible = "socionext,uniphier-gpio"; 287 reg = <0x55000080 0x8>; 288 gpio-controller; 289 #gpio-cells = <2>; 290 }; 291 292 port16x: gpio@55000088 { 293 compatible = "socionext,uniphier-gpio"; 294 reg = <0x55000088 0x8>; 295 gpio-controller; 296 #gpio-cells = <2>; 297 }; 298 299 port17x: gpio@550000a0 { 300 compatible = "socionext,uniphier-gpio"; 301 reg = <0x550000a0 0x8>; 302 gpio-controller; 303 #gpio-cells = <2>; 304 }; 305 306 port18x: gpio@550000a8 { 307 compatible = "socionext,uniphier-gpio"; 308 reg = <0x550000a8 0x8>; 309 gpio-controller; 310 #gpio-cells = <2>; 311 }; 312 313 port19x: gpio@550000b0 { 314 compatible = "socionext,uniphier-gpio"; 315 reg = <0x550000b0 0x8>; 316 gpio-controller; 317 #gpio-cells = <2>; 318 }; 319 320 port20x: gpio@550000b8 { 321 compatible = "socionext,uniphier-gpio"; 322 reg = <0x550000b8 0x8>; 323 gpio-controller; 324 #gpio-cells = <2>; 325 }; 326 327 port21x: gpio@550000c0 { 328 compatible = "socionext,uniphier-gpio"; 329 reg = <0x550000c0 0x8>; 330 gpio-controller; 331 #gpio-cells = <2>; 332 }; 333 334 port22x: gpio@550000c8 { 335 compatible = "socionext,uniphier-gpio"; 336 reg = <0x550000c8 0x8>; 337 gpio-controller; 338 #gpio-cells = <2>; 339 }; 340 341 port23x: gpio@550000d0 { 342 compatible = "socionext,uniphier-gpio"; 343 reg = <0x550000d0 0x8>; 344 gpio-controller; 345 #gpio-cells = <2>; 346 }; 347 348 port24x: gpio@550000d8 { 349 compatible = "socionext,uniphier-gpio"; 350 reg = <0x550000d8 0x8>; 351 gpio-controller; 352 #gpio-cells = <2>; 353 }; 354 355 port25x: gpio@550000e0 { 356 compatible = "socionext,uniphier-gpio"; 357 reg = <0x550000e0 0x8>; 358 gpio-controller; 359 #gpio-cells = <2>; 360 }; 361 362 port26x: gpio@550000e8 { 363 compatible = "socionext,uniphier-gpio"; 364 reg = <0x550000e8 0x8>; 365 gpio-controller; 366 #gpio-cells = <2>; 367 }; 368 369 port27x: gpio@550000f0 { 370 compatible = "socionext,uniphier-gpio"; 371 reg = <0x550000f0 0x8>; 372 gpio-controller; 373 #gpio-cells = <2>; 374 }; 375 376 port28x: gpio@550000f8 { 377 compatible = "socionext,uniphier-gpio"; 378 reg = <0x550000f8 0x8>; 379 gpio-controller; 380 #gpio-cells = <2>; 381 }; 382 383 i2c0: i2c@58780000 { 384 compatible = "socionext,uniphier-fi2c"; 385 status = "disabled"; 386 reg = <0x58780000 0x80>; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 interrupts = <0 41 4>; 390 pinctrl-names = "default"; 391 pinctrl-0 = <&pinctrl_i2c0>; 392 clocks = <&i2c_clk>; 393 clock-frequency = <100000>; 394 }; 395 396 i2c1: i2c@58781000 { 397 compatible = "socionext,uniphier-fi2c"; 398 status = "disabled"; 399 reg = <0x58781000 0x80>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 interrupts = <0 42 4>; 403 pinctrl-names = "default"; 404 pinctrl-0 = <&pinctrl_i2c1>; 405 clocks = <&i2c_clk>; 406 clock-frequency = <100000>; 407 }; 408 409 i2c2: i2c@58782000 { 410 compatible = "socionext,uniphier-fi2c"; 411 status = "disabled"; 412 reg = <0x58782000 0x80>; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 interrupts = <0 43 4>; 416 pinctrl-names = "default"; 417 pinctrl-0 = <&pinctrl_i2c2>; 418 clocks = <&i2c_clk>; 419 clock-frequency = <100000>; 420 }; 421 422 i2c3: i2c@58783000 { 423 compatible = "socionext,uniphier-fi2c"; 424 status = "disabled"; 425 reg = <0x58783000 0x80>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 interrupts = <0 44 4>; 429 pinctrl-names = "default"; 430 pinctrl-0 = <&pinctrl_i2c3>; 431 clocks = <&i2c_clk>; 432 clock-frequency = <100000>; 433 }; 434 435 /* chip-internal connection for DMD */ 436 i2c4: i2c@58784000 { 437 compatible = "socionext,uniphier-fi2c"; 438 reg = <0x58784000 0x80>; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 interrupts = <0 45 4>; 442 clocks = <&i2c_clk>; 443 clock-frequency = <400000>; 444 }; 445 446 /* chip-internal connection for STM */ 447 i2c5: i2c@58785000 { 448 compatible = "socionext,uniphier-fi2c"; 449 reg = <0x58785000 0x80>; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 interrupts = <0 25 4>; 453 clocks = <&i2c_clk>; 454 clock-frequency = <400000>; 455 }; 456 457 /* chip-internal connection for HDMI */ 458 i2c6: i2c@58786000 { 459 compatible = "socionext,uniphier-fi2c"; 460 reg = <0x58786000 0x80>; 461 #address-cells = <1>; 462 #size-cells = <0>; 463 interrupts = <0 26 4>; 464 clocks = <&i2c_clk>; 465 clock-frequency = <400000>; 466 }; 467 468 system_bus: system-bus@58c00000 { 469 compatible = "socionext,uniphier-system-bus"; 470 status = "disabled"; 471 reg = <0x58c00000 0x400>; 472 #address-cells = <2>; 473 #size-cells = <1>; 474 pinctrl-names = "default"; 475 pinctrl-0 = <&pinctrl_system_bus>; 476 }; 477 478 smpctrl@59800000 { 479 compatible = "socionext,uniphier-smpctrl"; 480 reg = <0x59801000 0x400>; 481 }; 482 483 sdctrl@59810000 { 484 compatible = "socionext,uniphier-pxs2-sdctrl", 485 "simple-mfd", "syscon"; 486 reg = <0x59810000 0x800>; 487 u-boot,dm-pre-reloc; 488 489 sd_clk: clock { 490 compatible = "socionext,uniphier-pxs2-sd-clock"; 491 #clock-cells = <1>; 492 }; 493 494 sd_rst: reset { 495 compatible = "socionext,uniphier-pxs2-sd-reset"; 496 #reset-cells = <1>; 497 }; 498 }; 499 500 perictrl@59820000 { 501 compatible = "socionext,uniphier-pxs2-perictrl", 502 "simple-mfd", "syscon"; 503 reg = <0x59820000 0x200>; 504 505 peri_clk: clock { 506 compatible = "socionext,uniphier-pxs2-peri-clock"; 507 #clock-cells = <1>; 508 }; 509 510 peri_rst: reset { 511 compatible = "socionext,uniphier-pxs2-peri-reset"; 512 #reset-cells = <1>; 513 }; 514 }; 515 516 emmc: sdhc@5a000000 { 517 compatible = "socionext,uniphier-sdhc"; 518 status = "disabled"; 519 reg = <0x5a000000 0x800>; 520 interrupts = <0 78 4>; 521 pinctrl-names = "default"; 522 pinctrl-0 = <&pinctrl_emmc>; 523 clocks = <&sd_clk 1>; 524 reset-names = "host"; 525 resets = <&sd_rst 1>; 526 bus-width = <8>; 527 non-removable; 528 cap-mmc-highspeed; 529 cap-mmc-hw-reset; 530 no-3-3-v; 531 }; 532 533 sd: sdhc@5a400000 { 534 compatible = "socionext,uniphier-sdhc"; 535 status = "disabled"; 536 reg = <0x5a400000 0x800>; 537 interrupts = <0 76 4>; 538 pinctrl-names = "default", "1.8v"; 539 pinctrl-0 = <&pinctrl_sd>; 540 pinctrl-1 = <&pinctrl_sd_1v8>; 541 clocks = <&sd_clk 0>; 542 reset-names = "host"; 543 resets = <&sd_rst 0>; 544 bus-width = <4>; 545 cap-sd-highspeed; 546 sd-uhs-sdr12; 547 sd-uhs-sdr25; 548 sd-uhs-sdr50; 549 }; 550 551 soc-glue@5f800000 { 552 compatible = "socionext,uniphier-pxs2-soc-glue", 553 "simple-mfd", "syscon"; 554 reg = <0x5f800000 0x2000>; 555 u-boot,dm-pre-reloc; 556 557 pinctrl: pinctrl { 558 compatible = "socionext,uniphier-pxs2-pinctrl"; 559 u-boot,dm-pre-reloc; 560 }; 561 }; 562 563 aidet@5fc20000 { 564 compatible = "simple-mfd", "syscon"; 565 reg = <0x5fc20000 0x200>; 566 }; 567 568 timer@60000200 { 569 compatible = "arm,cortex-a9-global-timer"; 570 reg = <0x60000200 0x20>; 571 interrupts = <1 11 0xf04>; 572 clocks = <&arm_timer_clk>; 573 }; 574 575 timer@60000600 { 576 compatible = "arm,cortex-a9-twd-timer"; 577 reg = <0x60000600 0x20>; 578 interrupts = <1 13 0xf04>; 579 clocks = <&arm_timer_clk>; 580 }; 581 582 intc: interrupt-controller@60001000 { 583 compatible = "arm,cortex-a9-gic"; 584 reg = <0x60001000 0x1000>, 585 <0x60000100 0x100>; 586 #interrupt-cells = <3>; 587 interrupt-controller; 588 }; 589 590 sysctrl@61840000 { 591 compatible = "socionext,uniphier-pxs2-sysctrl", 592 "simple-mfd", "syscon"; 593 reg = <0x61840000 0x4000>; 594 595 sys_clk: clock { 596 compatible = "socionext,uniphier-pxs2-clock"; 597 #clock-cells = <1>; 598 }; 599 600 sys_rst: reset { 601 compatible = "socionext,uniphier-pxs2-reset"; 602 #reset-cells = <1>; 603 }; 604 }; 605 606 usb0: usb@65b00000 { 607 compatible = "socionext,uniphier-pxs2-dwc3"; 608 status = "disabled"; 609 reg = <0x65b00000 0x1000>; 610 #address-cells = <1>; 611 #size-cells = <1>; 612 ranges; 613 pinctrl-names = "default"; 614 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; 615 dwc3@65a00000 { 616 compatible = "snps,dwc3"; 617 reg = <0x65a00000 0x10000>; 618 interrupts = <0 134 4>; 619 tx-fifo-resize; 620 }; 621 }; 622 623 usb1: usb@65d00000 { 624 compatible = "socionext,uniphier-pxs2-dwc3"; 625 status = "disabled"; 626 reg = <0x65d00000 0x1000>; 627 #address-cells = <1>; 628 #size-cells = <1>; 629 ranges; 630 pinctrl-names = "default"; 631 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; 632 dwc3@65c00000 { 633 compatible = "snps,dwc3"; 634 reg = <0x65c00000 0x10000>; 635 interrupts = <0 137 4>; 636 tx-fifo-resize; 637 }; 638 }; 639 640 nand: nand@68000000 { 641 compatible = "socionext,denali-nand-v5b"; 642 status = "disabled"; 643 reg-names = "nand_data", "denali_reg"; 644 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 645 interrupts = <0 65 4>; 646 pinctrl-names = "default"; 647 pinctrl-0 = <&pinctrl_nand>; 648 clocks = <&sys_clk 2>; 649 nand-ecc-strength = <8>; 650 }; 651 }; 652}; 653 654/include/ "uniphier-pinctrl.dtsi" 655