1/* 2 * Device Tree Source for UniPhier PXs2 SoC 3 * 4 * Copyright (C) 2015-2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 */ 9 10#include <dt-bindings/gpio/uniphier-gpio.h> 11#include <dt-bindings/thermal/thermal.h> 12 13/ { 14 compatible = "socionext,uniphier-pxs2"; 15 #address-cells = <1>; 16 #size-cells = <1>; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 22 cpu0: cpu@0 { 23 device_type = "cpu"; 24 compatible = "arm,cortex-a9"; 25 reg = <0>; 26 clocks = <&sys_clk 32>; 27 enable-method = "psci"; 28 next-level-cache = <&l2>; 29 operating-points-v2 = <&cpu_opp>; 30 #cooling-cells = <2>; 31 }; 32 33 cpu1: cpu@1 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a9"; 36 reg = <1>; 37 clocks = <&sys_clk 32>; 38 enable-method = "psci"; 39 next-level-cache = <&l2>; 40 operating-points-v2 = <&cpu_opp>; 41 }; 42 43 cpu2: cpu@2 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a9"; 46 reg = <2>; 47 clocks = <&sys_clk 32>; 48 enable-method = "psci"; 49 next-level-cache = <&l2>; 50 operating-points-v2 = <&cpu_opp>; 51 }; 52 53 cpu3: cpu@3 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a9"; 56 reg = <3>; 57 clocks = <&sys_clk 32>; 58 enable-method = "psci"; 59 next-level-cache = <&l2>; 60 operating-points-v2 = <&cpu_opp>; 61 }; 62 }; 63 64 cpu_opp: opp-table { 65 compatible = "operating-points-v2"; 66 opp-shared; 67 68 opp-100000000 { 69 opp-hz = /bits/ 64 <100000000>; 70 clock-latency-ns = <300>; 71 }; 72 opp-150000000 { 73 opp-hz = /bits/ 64 <150000000>; 74 clock-latency-ns = <300>; 75 }; 76 opp-200000000 { 77 opp-hz = /bits/ 64 <200000000>; 78 clock-latency-ns = <300>; 79 }; 80 opp-300000000 { 81 opp-hz = /bits/ 64 <300000000>; 82 clock-latency-ns = <300>; 83 }; 84 opp-400000000 { 85 opp-hz = /bits/ 64 <400000000>; 86 clock-latency-ns = <300>; 87 }; 88 opp-600000000 { 89 opp-hz = /bits/ 64 <600000000>; 90 clock-latency-ns = <300>; 91 }; 92 opp-800000000 { 93 opp-hz = /bits/ 64 <800000000>; 94 clock-latency-ns = <300>; 95 }; 96 opp-1200000000 { 97 opp-hz = /bits/ 64 <1200000000>; 98 clock-latency-ns = <300>; 99 }; 100 }; 101 102 psci { 103 compatible = "arm,psci-0.2"; 104 method = "smc"; 105 }; 106 107 clocks { 108 refclk: ref { 109 compatible = "fixed-clock"; 110 #clock-cells = <0>; 111 clock-frequency = <25000000>; 112 }; 113 114 arm_timer_clk: arm-timer { 115 #clock-cells = <0>; 116 compatible = "fixed-clock"; 117 clock-frequency = <50000000>; 118 }; 119 }; 120 121 thermal-zones { 122 cpu-thermal { 123 polling-delay-passive = <250>; /* 250ms */ 124 polling-delay = <1000>; /* 1000ms */ 125 thermal-sensors = <&pvtctl>; 126 127 trips { 128 cpu_crit: cpu-crit { 129 temperature = <95000>; /* 95C */ 130 hysteresis = <2000>; 131 type = "critical"; 132 }; 133 cpu_alert: cpu-alert { 134 temperature = <85000>; /* 85C */ 135 hysteresis = <2000>; 136 type = "passive"; 137 }; 138 }; 139 140 cooling-maps { 141 map { 142 trip = <&cpu_alert>; 143 cooling-device = <&cpu0 144 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 145 }; 146 }; 147 }; 148 }; 149 150 soc { 151 compatible = "simple-bus"; 152 #address-cells = <1>; 153 #size-cells = <1>; 154 ranges; 155 interrupt-parent = <&intc>; 156 157 l2: l2-cache@500c0000 { 158 compatible = "socionext,uniphier-system-cache"; 159 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, 160 <0x506c0000 0x400>; 161 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; 162 cache-unified; 163 cache-size = <(1280 * 1024)>; 164 cache-sets = <512>; 165 cache-line-size = <128>; 166 cache-level = <2>; 167 }; 168 169 serial0: serial@54006800 { 170 compatible = "socionext,uniphier-uart"; 171 status = "disabled"; 172 reg = <0x54006800 0x40>; 173 interrupts = <0 33 4>; 174 pinctrl-names = "default"; 175 pinctrl-0 = <&pinctrl_uart0>; 176 clocks = <&peri_clk 0>; 177 clock-frequency = <88900000>; 178 resets = <&peri_rst 0>; 179 }; 180 181 serial1: serial@54006900 { 182 compatible = "socionext,uniphier-uart"; 183 status = "disabled"; 184 reg = <0x54006900 0x40>; 185 interrupts = <0 35 4>; 186 pinctrl-names = "default"; 187 pinctrl-0 = <&pinctrl_uart1>; 188 clocks = <&peri_clk 1>; 189 clock-frequency = <88900000>; 190 resets = <&peri_rst 1>; 191 }; 192 193 serial2: serial@54006a00 { 194 compatible = "socionext,uniphier-uart"; 195 status = "disabled"; 196 reg = <0x54006a00 0x40>; 197 interrupts = <0 37 4>; 198 pinctrl-names = "default"; 199 pinctrl-0 = <&pinctrl_uart2>; 200 clocks = <&peri_clk 2>; 201 clock-frequency = <88900000>; 202 resets = <&peri_rst 2>; 203 }; 204 205 serial3: serial@54006b00 { 206 compatible = "socionext,uniphier-uart"; 207 status = "disabled"; 208 reg = <0x54006b00 0x40>; 209 interrupts = <0 177 4>; 210 pinctrl-names = "default"; 211 pinctrl-0 = <&pinctrl_uart3>; 212 clocks = <&peri_clk 3>; 213 clock-frequency = <88900000>; 214 resets = <&peri_rst 3>; 215 }; 216 217 gpio: gpio@55000000 { 218 compatible = "socionext,uniphier-gpio"; 219 reg = <0x55000000 0x200>; 220 interrupt-parent = <&aidet>; 221 interrupt-controller; 222 #interrupt-cells = <2>; 223 gpio-controller; 224 #gpio-cells = <2>; 225 gpio-ranges = <&pinctrl 0 0 0>, 226 <&pinctrl 96 0 0>; 227 gpio-ranges-group-names = "gpio_range0", 228 "gpio_range1"; 229 ngpios = <232>; 230 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 231 <21 217 3>; 232 }; 233 234 i2c0: i2c@58780000 { 235 compatible = "socionext,uniphier-fi2c"; 236 status = "disabled"; 237 reg = <0x58780000 0x80>; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 interrupts = <0 41 4>; 241 pinctrl-names = "default"; 242 pinctrl-0 = <&pinctrl_i2c0>; 243 clocks = <&peri_clk 4>; 244 resets = <&peri_rst 4>; 245 clock-frequency = <100000>; 246 }; 247 248 i2c1: i2c@58781000 { 249 compatible = "socionext,uniphier-fi2c"; 250 status = "disabled"; 251 reg = <0x58781000 0x80>; 252 #address-cells = <1>; 253 #size-cells = <0>; 254 interrupts = <0 42 4>; 255 pinctrl-names = "default"; 256 pinctrl-0 = <&pinctrl_i2c1>; 257 clocks = <&peri_clk 5>; 258 resets = <&peri_rst 5>; 259 clock-frequency = <100000>; 260 }; 261 262 i2c2: i2c@58782000 { 263 compatible = "socionext,uniphier-fi2c"; 264 status = "disabled"; 265 reg = <0x58782000 0x80>; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 interrupts = <0 43 4>; 269 pinctrl-names = "default"; 270 pinctrl-0 = <&pinctrl_i2c2>; 271 clocks = <&peri_clk 6>; 272 resets = <&peri_rst 6>; 273 clock-frequency = <100000>; 274 }; 275 276 i2c3: i2c@58783000 { 277 compatible = "socionext,uniphier-fi2c"; 278 status = "disabled"; 279 reg = <0x58783000 0x80>; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 interrupts = <0 44 4>; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&pinctrl_i2c3>; 285 clocks = <&peri_clk 7>; 286 resets = <&peri_rst 7>; 287 clock-frequency = <100000>; 288 }; 289 290 /* chip-internal connection for DMD */ 291 i2c4: i2c@58784000 { 292 compatible = "socionext,uniphier-fi2c"; 293 reg = <0x58784000 0x80>; 294 #address-cells = <1>; 295 #size-cells = <0>; 296 interrupts = <0 45 4>; 297 clocks = <&peri_clk 8>; 298 resets = <&peri_rst 8>; 299 clock-frequency = <400000>; 300 }; 301 302 /* chip-internal connection for STM */ 303 i2c5: i2c@58785000 { 304 compatible = "socionext,uniphier-fi2c"; 305 reg = <0x58785000 0x80>; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 interrupts = <0 25 4>; 309 clocks = <&peri_clk 9>; 310 resets = <&peri_rst 9>; 311 clock-frequency = <400000>; 312 }; 313 314 /* chip-internal connection for HDMI */ 315 i2c6: i2c@58786000 { 316 compatible = "socionext,uniphier-fi2c"; 317 reg = <0x58786000 0x80>; 318 #address-cells = <1>; 319 #size-cells = <0>; 320 interrupts = <0 26 4>; 321 clocks = <&peri_clk 10>; 322 resets = <&peri_rst 10>; 323 clock-frequency = <400000>; 324 }; 325 326 system_bus: system-bus@58c00000 { 327 compatible = "socionext,uniphier-system-bus"; 328 status = "disabled"; 329 reg = <0x58c00000 0x400>; 330 #address-cells = <2>; 331 #size-cells = <1>; 332 pinctrl-names = "default"; 333 pinctrl-0 = <&pinctrl_system_bus>; 334 }; 335 336 smpctrl@59801000 { 337 compatible = "socionext,uniphier-smpctrl"; 338 reg = <0x59801000 0x400>; 339 }; 340 341 sdctrl@59810000 { 342 compatible = "socionext,uniphier-pxs2-sdctrl", 343 "simple-mfd", "syscon"; 344 reg = <0x59810000 0x400>; 345 346 sd_clk: clock { 347 compatible = "socionext,uniphier-pxs2-sd-clock"; 348 #clock-cells = <1>; 349 }; 350 351 sd_rst: reset { 352 compatible = "socionext,uniphier-pxs2-sd-reset"; 353 #reset-cells = <1>; 354 }; 355 }; 356 357 perictrl@59820000 { 358 compatible = "socionext,uniphier-pxs2-perictrl", 359 "simple-mfd", "syscon"; 360 reg = <0x59820000 0x200>; 361 362 peri_clk: clock { 363 compatible = "socionext,uniphier-pxs2-peri-clock"; 364 #clock-cells = <1>; 365 }; 366 367 peri_rst: reset { 368 compatible = "socionext,uniphier-pxs2-peri-reset"; 369 #reset-cells = <1>; 370 }; 371 }; 372 373 emmc: sdhc@5a000000 { 374 compatible = "socionext,uniphier-sdhc"; 375 status = "disabled"; 376 reg = <0x5a000000 0x800>; 377 interrupts = <0 78 4>; 378 pinctrl-names = "default"; 379 pinctrl-0 = <&pinctrl_emmc>; 380 clocks = <&sd_clk 1>; 381 reset-names = "host"; 382 resets = <&sd_rst 1>; 383 bus-width = <8>; 384 non-removable; 385 cap-mmc-highspeed; 386 cap-mmc-hw-reset; 387 no-3-3-v; 388 }; 389 390 sd: sdhc@5a400000 { 391 compatible = "socionext,uniphier-sdhc"; 392 status = "disabled"; 393 reg = <0x5a400000 0x800>; 394 interrupts = <0 76 4>; 395 pinctrl-names = "default", "1.8v"; 396 pinctrl-0 = <&pinctrl_sd>; 397 pinctrl-1 = <&pinctrl_sd_1v8>; 398 clocks = <&sd_clk 0>; 399 reset-names = "host"; 400 resets = <&sd_rst 0>; 401 bus-width = <4>; 402 cap-sd-highspeed; 403 sd-uhs-sdr12; 404 sd-uhs-sdr25; 405 sd-uhs-sdr50; 406 }; 407 408 soc-glue@5f800000 { 409 compatible = "socionext,uniphier-pxs2-soc-glue", 410 "simple-mfd", "syscon"; 411 reg = <0x5f800000 0x2000>; 412 413 pinctrl: pinctrl { 414 compatible = "socionext,uniphier-pxs2-pinctrl"; 415 }; 416 }; 417 418 aidet: aidet@5fc20000 { 419 compatible = "socionext,uniphier-pxs2-aidet"; 420 reg = <0x5fc20000 0x200>; 421 interrupt-controller; 422 #interrupt-cells = <2>; 423 }; 424 425 timer@60000200 { 426 compatible = "arm,cortex-a9-global-timer"; 427 reg = <0x60000200 0x20>; 428 interrupts = <1 11 0xf04>; 429 clocks = <&arm_timer_clk>; 430 }; 431 432 timer@60000600 { 433 compatible = "arm,cortex-a9-twd-timer"; 434 reg = <0x60000600 0x20>; 435 interrupts = <1 13 0xf04>; 436 clocks = <&arm_timer_clk>; 437 }; 438 439 intc: interrupt-controller@60001000 { 440 compatible = "arm,cortex-a9-gic"; 441 reg = <0x60001000 0x1000>, 442 <0x60000100 0x100>; 443 #interrupt-cells = <3>; 444 interrupt-controller; 445 }; 446 447 sysctrl@61840000 { 448 compatible = "socionext,uniphier-pxs2-sysctrl", 449 "simple-mfd", "syscon"; 450 reg = <0x61840000 0x10000>; 451 452 sys_clk: clock { 453 compatible = "socionext,uniphier-pxs2-clock"; 454 #clock-cells = <1>; 455 }; 456 457 sys_rst: reset { 458 compatible = "socionext,uniphier-pxs2-reset"; 459 #reset-cells = <1>; 460 }; 461 462 pvtctl: pvtctl { 463 compatible = "socionext,uniphier-pxs2-thermal"; 464 interrupts = <0 3 4>; 465 #thermal-sensor-cells = <0>; 466 socionext,tmod-calibration = <0x0f86 0x6844>; 467 }; 468 }; 469 470 usb0: usb@65b00000 { 471 compatible = "socionext,uniphier-pxs2-dwc3"; 472 status = "disabled"; 473 reg = <0x65b00000 0x1000>; 474 #address-cells = <1>; 475 #size-cells = <1>; 476 ranges; 477 pinctrl-names = "default"; 478 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; 479 dwc3@65a00000 { 480 compatible = "snps,dwc3"; 481 reg = <0x65a00000 0x10000>; 482 interrupts = <0 134 4>; 483 dr_mode = "host"; 484 tx-fifo-resize; 485 }; 486 }; 487 488 usb1: usb@65d00000 { 489 compatible = "socionext,uniphier-pxs2-dwc3"; 490 status = "disabled"; 491 reg = <0x65d00000 0x1000>; 492 #address-cells = <1>; 493 #size-cells = <1>; 494 ranges; 495 pinctrl-names = "default"; 496 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; 497 dwc3@65c00000 { 498 compatible = "snps,dwc3"; 499 reg = <0x65c00000 0x10000>; 500 interrupts = <0 137 4>; 501 dr_mode = "host"; 502 tx-fifo-resize; 503 }; 504 }; 505 506 nand: nand@68000000 { 507 compatible = "socionext,uniphier-denali-nand-v5b"; 508 status = "disabled"; 509 reg-names = "nand_data", "denali_reg"; 510 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 511 interrupts = <0 65 4>; 512 pinctrl-names = "default"; 513 pinctrl-0 = <&pinctrl_nand2cs>; 514 clocks = <&sys_clk 2>; 515 resets = <&sys_rst 2>; 516 }; 517 }; 518}; 519 520#include "uniphier-pinctrl.dtsi" 521