1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Device Tree Source for UniPhier PXs2 SoC 4// 5// Copyright (C) 2015-2016 Socionext Inc. 6// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 8#include <dt-bindings/gpio/uniphier-gpio.h> 9#include <dt-bindings/thermal/thermal.h> 10 11/ { 12 compatible = "socionext,uniphier-pxs2"; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 device_type = "cpu"; 22 compatible = "arm,cortex-a9"; 23 reg = <0>; 24 clocks = <&sys_clk 32>; 25 enable-method = "psci"; 26 next-level-cache = <&l2>; 27 operating-points-v2 = <&cpu_opp>; 28 #cooling-cells = <2>; 29 }; 30 31 cpu1: cpu@1 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a9"; 34 reg = <1>; 35 clocks = <&sys_clk 32>; 36 enable-method = "psci"; 37 next-level-cache = <&l2>; 38 operating-points-v2 = <&cpu_opp>; 39 }; 40 41 cpu2: cpu@2 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a9"; 44 reg = <2>; 45 clocks = <&sys_clk 32>; 46 enable-method = "psci"; 47 next-level-cache = <&l2>; 48 operating-points-v2 = <&cpu_opp>; 49 }; 50 51 cpu3: cpu@3 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a9"; 54 reg = <3>; 55 clocks = <&sys_clk 32>; 56 enable-method = "psci"; 57 next-level-cache = <&l2>; 58 operating-points-v2 = <&cpu_opp>; 59 }; 60 }; 61 62 cpu_opp: opp-table { 63 compatible = "operating-points-v2"; 64 opp-shared; 65 66 opp-100000000 { 67 opp-hz = /bits/ 64 <100000000>; 68 clock-latency-ns = <300>; 69 }; 70 opp-150000000 { 71 opp-hz = /bits/ 64 <150000000>; 72 clock-latency-ns = <300>; 73 }; 74 opp-200000000 { 75 opp-hz = /bits/ 64 <200000000>; 76 clock-latency-ns = <300>; 77 }; 78 opp-300000000 { 79 opp-hz = /bits/ 64 <300000000>; 80 clock-latency-ns = <300>; 81 }; 82 opp-400000000 { 83 opp-hz = /bits/ 64 <400000000>; 84 clock-latency-ns = <300>; 85 }; 86 opp-600000000 { 87 opp-hz = /bits/ 64 <600000000>; 88 clock-latency-ns = <300>; 89 }; 90 opp-800000000 { 91 opp-hz = /bits/ 64 <800000000>; 92 clock-latency-ns = <300>; 93 }; 94 opp-1200000000 { 95 opp-hz = /bits/ 64 <1200000000>; 96 clock-latency-ns = <300>; 97 }; 98 }; 99 100 psci { 101 compatible = "arm,psci-0.2"; 102 method = "smc"; 103 }; 104 105 clocks { 106 refclk: ref { 107 compatible = "fixed-clock"; 108 #clock-cells = <0>; 109 clock-frequency = <25000000>; 110 }; 111 112 arm_timer_clk: arm-timer { 113 #clock-cells = <0>; 114 compatible = "fixed-clock"; 115 clock-frequency = <50000000>; 116 }; 117 }; 118 119 thermal-zones { 120 cpu-thermal { 121 polling-delay-passive = <250>; /* 250ms */ 122 polling-delay = <1000>; /* 1000ms */ 123 thermal-sensors = <&pvtctl>; 124 125 trips { 126 cpu_crit: cpu-crit { 127 temperature = <95000>; /* 95C */ 128 hysteresis = <2000>; 129 type = "critical"; 130 }; 131 cpu_alert: cpu-alert { 132 temperature = <85000>; /* 85C */ 133 hysteresis = <2000>; 134 type = "passive"; 135 }; 136 }; 137 138 cooling-maps { 139 map { 140 trip = <&cpu_alert>; 141 cooling-device = <&cpu0 142 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 143 }; 144 }; 145 }; 146 }; 147 148 soc { 149 compatible = "simple-bus"; 150 #address-cells = <1>; 151 #size-cells = <1>; 152 ranges; 153 interrupt-parent = <&intc>; 154 155 l2: l2-cache@500c0000 { 156 compatible = "socionext,uniphier-system-cache"; 157 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, 158 <0x506c0000 0x400>; 159 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; 160 cache-unified; 161 cache-size = <(1280 * 1024)>; 162 cache-sets = <512>; 163 cache-line-size = <128>; 164 cache-level = <2>; 165 }; 166 167 serial0: serial@54006800 { 168 compatible = "socionext,uniphier-uart"; 169 status = "disabled"; 170 reg = <0x54006800 0x40>; 171 interrupts = <0 33 4>; 172 pinctrl-names = "default"; 173 pinctrl-0 = <&pinctrl_uart0>; 174 clocks = <&peri_clk 0>; 175 clock-frequency = <88900000>; 176 resets = <&peri_rst 0>; 177 }; 178 179 serial1: serial@54006900 { 180 compatible = "socionext,uniphier-uart"; 181 status = "disabled"; 182 reg = <0x54006900 0x40>; 183 interrupts = <0 35 4>; 184 pinctrl-names = "default"; 185 pinctrl-0 = <&pinctrl_uart1>; 186 clocks = <&peri_clk 1>; 187 clock-frequency = <88900000>; 188 resets = <&peri_rst 1>; 189 }; 190 191 serial2: serial@54006a00 { 192 compatible = "socionext,uniphier-uart"; 193 status = "disabled"; 194 reg = <0x54006a00 0x40>; 195 interrupts = <0 37 4>; 196 pinctrl-names = "default"; 197 pinctrl-0 = <&pinctrl_uart2>; 198 clocks = <&peri_clk 2>; 199 clock-frequency = <88900000>; 200 resets = <&peri_rst 2>; 201 }; 202 203 serial3: serial@54006b00 { 204 compatible = "socionext,uniphier-uart"; 205 status = "disabled"; 206 reg = <0x54006b00 0x40>; 207 interrupts = <0 177 4>; 208 pinctrl-names = "default"; 209 pinctrl-0 = <&pinctrl_uart3>; 210 clocks = <&peri_clk 3>; 211 clock-frequency = <88900000>; 212 resets = <&peri_rst 3>; 213 }; 214 215 gpio: gpio@55000000 { 216 compatible = "socionext,uniphier-gpio"; 217 reg = <0x55000000 0x200>; 218 interrupt-parent = <&aidet>; 219 interrupt-controller; 220 #interrupt-cells = <2>; 221 gpio-controller; 222 #gpio-cells = <2>; 223 gpio-ranges = <&pinctrl 0 0 0>, 224 <&pinctrl 96 0 0>; 225 gpio-ranges-group-names = "gpio_range0", 226 "gpio_range1"; 227 ngpios = <232>; 228 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 229 <21 217 3>; 230 }; 231 232 audio@56000000 { 233 compatible = "socionext,uniphier-pxs2-aio"; 234 reg = <0x56000000 0x80000>; 235 interrupts = <0 144 4>; 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_ain1>, 238 <&pinctrl_ain2>, 239 <&pinctrl_ainiec1>, 240 <&pinctrl_aout2>, 241 <&pinctrl_aout3>, 242 <&pinctrl_aoutiec1>, 243 <&pinctrl_aoutiec2>; 244 clock-names = "aio"; 245 clocks = <&sys_clk 40>; 246 reset-names = "aio"; 247 resets = <&sys_rst 40>; 248 #sound-dai-cells = <1>; 249 socionext,syscon = <&soc_glue>; 250 251 i2s_port0: port@0 { 252 i2s_hdmi: endpoint { 253 }; 254 }; 255 256 i2s_port1: port@1 { 257 i2s_line: endpoint { 258 }; 259 }; 260 261 i2s_port2: port@2 { 262 i2s_aux: endpoint { 263 }; 264 }; 265 266 spdif_port0: port@3 { 267 spdif_hiecout1: endpoint { 268 }; 269 }; 270 271 spdif_port1: port@4 { 272 spdif_iecout1: endpoint { 273 }; 274 }; 275 276 comp_spdif_port0: port@5 { 277 comp_spdif_hiecout1: endpoint { 278 }; 279 }; 280 281 comp_spdif_port1: port@6 { 282 comp_spdif_iecout1: endpoint { 283 }; 284 }; 285 }; 286 287 i2c0: i2c@58780000 { 288 compatible = "socionext,uniphier-fi2c"; 289 status = "disabled"; 290 reg = <0x58780000 0x80>; 291 #address-cells = <1>; 292 #size-cells = <0>; 293 interrupts = <0 41 4>; 294 pinctrl-names = "default"; 295 pinctrl-0 = <&pinctrl_i2c0>; 296 clocks = <&peri_clk 4>; 297 resets = <&peri_rst 4>; 298 clock-frequency = <100000>; 299 }; 300 301 i2c1: i2c@58781000 { 302 compatible = "socionext,uniphier-fi2c"; 303 status = "disabled"; 304 reg = <0x58781000 0x80>; 305 #address-cells = <1>; 306 #size-cells = <0>; 307 interrupts = <0 42 4>; 308 pinctrl-names = "default"; 309 pinctrl-0 = <&pinctrl_i2c1>; 310 clocks = <&peri_clk 5>; 311 resets = <&peri_rst 5>; 312 clock-frequency = <100000>; 313 }; 314 315 i2c2: i2c@58782000 { 316 compatible = "socionext,uniphier-fi2c"; 317 status = "disabled"; 318 reg = <0x58782000 0x80>; 319 #address-cells = <1>; 320 #size-cells = <0>; 321 interrupts = <0 43 4>; 322 pinctrl-names = "default"; 323 pinctrl-0 = <&pinctrl_i2c2>; 324 clocks = <&peri_clk 6>; 325 resets = <&peri_rst 6>; 326 clock-frequency = <100000>; 327 }; 328 329 i2c3: i2c@58783000 { 330 compatible = "socionext,uniphier-fi2c"; 331 status = "disabled"; 332 reg = <0x58783000 0x80>; 333 #address-cells = <1>; 334 #size-cells = <0>; 335 interrupts = <0 44 4>; 336 pinctrl-names = "default"; 337 pinctrl-0 = <&pinctrl_i2c3>; 338 clocks = <&peri_clk 7>; 339 resets = <&peri_rst 7>; 340 clock-frequency = <100000>; 341 }; 342 343 /* chip-internal connection for DMD */ 344 i2c4: i2c@58784000 { 345 compatible = "socionext,uniphier-fi2c"; 346 reg = <0x58784000 0x80>; 347 #address-cells = <1>; 348 #size-cells = <0>; 349 interrupts = <0 45 4>; 350 clocks = <&peri_clk 8>; 351 resets = <&peri_rst 8>; 352 clock-frequency = <400000>; 353 }; 354 355 /* chip-internal connection for STM */ 356 i2c5: i2c@58785000 { 357 compatible = "socionext,uniphier-fi2c"; 358 reg = <0x58785000 0x80>; 359 #address-cells = <1>; 360 #size-cells = <0>; 361 interrupts = <0 25 4>; 362 clocks = <&peri_clk 9>; 363 resets = <&peri_rst 9>; 364 clock-frequency = <400000>; 365 }; 366 367 /* chip-internal connection for HDMI */ 368 i2c6: i2c@58786000 { 369 compatible = "socionext,uniphier-fi2c"; 370 reg = <0x58786000 0x80>; 371 #address-cells = <1>; 372 #size-cells = <0>; 373 interrupts = <0 26 4>; 374 clocks = <&peri_clk 10>; 375 resets = <&peri_rst 10>; 376 clock-frequency = <400000>; 377 }; 378 379 system_bus: system-bus@58c00000 { 380 compatible = "socionext,uniphier-system-bus"; 381 status = "disabled"; 382 reg = <0x58c00000 0x400>; 383 #address-cells = <2>; 384 #size-cells = <1>; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&pinctrl_system_bus>; 387 }; 388 389 smpctrl@59801000 { 390 compatible = "socionext,uniphier-smpctrl"; 391 reg = <0x59801000 0x400>; 392 }; 393 394 sdctrl@59810000 { 395 compatible = "socionext,uniphier-pxs2-sdctrl", 396 "simple-mfd", "syscon"; 397 reg = <0x59810000 0x400>; 398 399 sd_clk: clock { 400 compatible = "socionext,uniphier-pxs2-sd-clock"; 401 #clock-cells = <1>; 402 }; 403 404 sd_rst: reset { 405 compatible = "socionext,uniphier-pxs2-sd-reset"; 406 #reset-cells = <1>; 407 }; 408 }; 409 410 perictrl@59820000 { 411 compatible = "socionext,uniphier-pxs2-perictrl", 412 "simple-mfd", "syscon"; 413 reg = <0x59820000 0x200>; 414 415 peri_clk: clock { 416 compatible = "socionext,uniphier-pxs2-peri-clock"; 417 #clock-cells = <1>; 418 }; 419 420 peri_rst: reset { 421 compatible = "socionext,uniphier-pxs2-peri-reset"; 422 #reset-cells = <1>; 423 }; 424 }; 425 426 emmc: sdhc@5a000000 { 427 compatible = "socionext,uniphier-sdhc"; 428 status = "disabled"; 429 reg = <0x5a000000 0x800>; 430 interrupts = <0 78 4>; 431 pinctrl-names = "default"; 432 pinctrl-0 = <&pinctrl_emmc>; 433 clocks = <&sd_clk 1>; 434 reset-names = "host"; 435 resets = <&sd_rst 1>; 436 bus-width = <8>; 437 non-removable; 438 cap-mmc-highspeed; 439 cap-mmc-hw-reset; 440 no-3-3-v; 441 }; 442 443 sd: sdhc@5a400000 { 444 compatible = "socionext,uniphier-sdhc"; 445 status = "disabled"; 446 reg = <0x5a400000 0x800>; 447 interrupts = <0 76 4>; 448 pinctrl-names = "default", "1.8v"; 449 pinctrl-0 = <&pinctrl_sd>; 450 pinctrl-1 = <&pinctrl_sd_1v8>; 451 clocks = <&sd_clk 0>; 452 reset-names = "host"; 453 resets = <&sd_rst 0>; 454 bus-width = <4>; 455 cap-sd-highspeed; 456 sd-uhs-sdr12; 457 sd-uhs-sdr25; 458 sd-uhs-sdr50; 459 }; 460 461 soc_glue: soc-glue@5f800000 { 462 compatible = "socionext,uniphier-pxs2-soc-glue", 463 "simple-mfd", "syscon"; 464 reg = <0x5f800000 0x2000>; 465 466 pinctrl: pinctrl { 467 compatible = "socionext,uniphier-pxs2-pinctrl"; 468 }; 469 }; 470 471 soc-glue@5f900000 { 472 compatible = "socionext,uniphier-pxs2-soc-glue-debug", 473 "simple-mfd"; 474 #address-cells = <1>; 475 #size-cells = <1>; 476 ranges = <0 0x5f900000 0x2000>; 477 478 efuse@100 { 479 compatible = "socionext,uniphier-efuse"; 480 reg = <0x100 0x28>; 481 }; 482 483 efuse@200 { 484 compatible = "socionext,uniphier-efuse"; 485 reg = <0x200 0x58>; 486 }; 487 }; 488 489 aidet: aidet@5fc20000 { 490 compatible = "socionext,uniphier-pxs2-aidet"; 491 reg = <0x5fc20000 0x200>; 492 interrupt-controller; 493 #interrupt-cells = <2>; 494 }; 495 496 timer@60000200 { 497 compatible = "arm,cortex-a9-global-timer"; 498 reg = <0x60000200 0x20>; 499 interrupts = <1 11 0xf04>; 500 clocks = <&arm_timer_clk>; 501 }; 502 503 timer@60000600 { 504 compatible = "arm,cortex-a9-twd-timer"; 505 reg = <0x60000600 0x20>; 506 interrupts = <1 13 0xf04>; 507 clocks = <&arm_timer_clk>; 508 }; 509 510 intc: interrupt-controller@60001000 { 511 compatible = "arm,cortex-a9-gic"; 512 reg = <0x60001000 0x1000>, 513 <0x60000100 0x100>; 514 #interrupt-cells = <3>; 515 interrupt-controller; 516 }; 517 518 sysctrl@61840000 { 519 compatible = "socionext,uniphier-pxs2-sysctrl", 520 "simple-mfd", "syscon"; 521 reg = <0x61840000 0x10000>; 522 523 sys_clk: clock { 524 compatible = "socionext,uniphier-pxs2-clock"; 525 #clock-cells = <1>; 526 }; 527 528 sys_rst: reset { 529 compatible = "socionext,uniphier-pxs2-reset"; 530 #reset-cells = <1>; 531 }; 532 533 pvtctl: pvtctl { 534 compatible = "socionext,uniphier-pxs2-thermal"; 535 interrupts = <0 3 4>; 536 #thermal-sensor-cells = <0>; 537 socionext,tmod-calibration = <0x0f86 0x6844>; 538 }; 539 }; 540 541 eth: ethernet@65000000 { 542 compatible = "socionext,uniphier-pxs2-ave4"; 543 status = "disabled"; 544 reg = <0x65000000 0x8500>; 545 interrupts = <0 66 4>; 546 pinctrl-names = "default"; 547 pinctrl-0 = <&pinctrl_ether_rgmii>; 548 clocks = <&sys_clk 6>; 549 resets = <&sys_rst 6>; 550 phy-mode = "rgmii"; 551 local-mac-address = [00 00 00 00 00 00]; 552 553 mdio: mdio { 554 #address-cells = <1>; 555 #size-cells = <0>; 556 }; 557 }; 558 559 usb0: usb@65b00000 { 560 compatible = "socionext,uniphier-pxs2-dwc3"; 561 status = "disabled"; 562 reg = <0x65b00000 0x1000>; 563 #address-cells = <1>; 564 #size-cells = <1>; 565 ranges; 566 pinctrl-names = "default"; 567 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; 568 dwc3@65a00000 { 569 compatible = "snps,dwc3"; 570 reg = <0x65a00000 0x10000>; 571 interrupts = <0 134 4>; 572 dr_mode = "host"; 573 tx-fifo-resize; 574 }; 575 }; 576 577 usb1: usb@65d00000 { 578 compatible = "socionext,uniphier-pxs2-dwc3"; 579 status = "disabled"; 580 reg = <0x65d00000 0x1000>; 581 #address-cells = <1>; 582 #size-cells = <1>; 583 ranges; 584 pinctrl-names = "default"; 585 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; 586 dwc3@65c00000 { 587 compatible = "snps,dwc3"; 588 reg = <0x65c00000 0x10000>; 589 interrupts = <0 137 4>; 590 dr_mode = "host"; 591 tx-fifo-resize; 592 }; 593 }; 594 595 nand: nand@68000000 { 596 compatible = "socionext,uniphier-denali-nand-v5b"; 597 status = "disabled"; 598 reg-names = "nand_data", "denali_reg"; 599 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 600 interrupts = <0 65 4>; 601 pinctrl-names = "default"; 602 pinctrl-0 = <&pinctrl_nand2cs>; 603 clocks = <&sys_clk 2>; 604 resets = <&sys_rst 2>; 605 }; 606 }; 607}; 608 609#include "uniphier-pinctrl.dtsi" 610