1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Device Tree Source for UniPhier PXs2 SoC 4// 5// Copyright (C) 2015-2016 Socionext Inc. 6// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 8#include <dt-bindings/gpio/uniphier-gpio.h> 9#include <dt-bindings/thermal/thermal.h> 10 11/ { 12 compatible = "socionext,uniphier-pxs2"; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 device_type = "cpu"; 22 compatible = "arm,cortex-a9"; 23 reg = <0>; 24 clocks = <&sys_clk 32>; 25 enable-method = "psci"; 26 next-level-cache = <&l2>; 27 operating-points-v2 = <&cpu_opp>; 28 #cooling-cells = <2>; 29 }; 30 31 cpu1: cpu@1 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a9"; 34 reg = <1>; 35 clocks = <&sys_clk 32>; 36 enable-method = "psci"; 37 next-level-cache = <&l2>; 38 operating-points-v2 = <&cpu_opp>; 39 #cooling-cells = <2>; 40 }; 41 42 cpu2: cpu@2 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a9"; 45 reg = <2>; 46 clocks = <&sys_clk 32>; 47 enable-method = "psci"; 48 next-level-cache = <&l2>; 49 operating-points-v2 = <&cpu_opp>; 50 #cooling-cells = <2>; 51 }; 52 53 cpu3: cpu@3 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a9"; 56 reg = <3>; 57 clocks = <&sys_clk 32>; 58 enable-method = "psci"; 59 next-level-cache = <&l2>; 60 operating-points-v2 = <&cpu_opp>; 61 #cooling-cells = <2>; 62 }; 63 }; 64 65 cpu_opp: opp-table { 66 compatible = "operating-points-v2"; 67 opp-shared; 68 69 opp-100000000 { 70 opp-hz = /bits/ 64 <100000000>; 71 clock-latency-ns = <300>; 72 }; 73 opp-150000000 { 74 opp-hz = /bits/ 64 <150000000>; 75 clock-latency-ns = <300>; 76 }; 77 opp-200000000 { 78 opp-hz = /bits/ 64 <200000000>; 79 clock-latency-ns = <300>; 80 }; 81 opp-300000000 { 82 opp-hz = /bits/ 64 <300000000>; 83 clock-latency-ns = <300>; 84 }; 85 opp-400000000 { 86 opp-hz = /bits/ 64 <400000000>; 87 clock-latency-ns = <300>; 88 }; 89 opp-600000000 { 90 opp-hz = /bits/ 64 <600000000>; 91 clock-latency-ns = <300>; 92 }; 93 opp-800000000 { 94 opp-hz = /bits/ 64 <800000000>; 95 clock-latency-ns = <300>; 96 }; 97 opp-1200000000 { 98 opp-hz = /bits/ 64 <1200000000>; 99 clock-latency-ns = <300>; 100 }; 101 }; 102 103 psci { 104 compatible = "arm,psci-0.2"; 105 method = "smc"; 106 }; 107 108 clocks { 109 refclk: ref { 110 compatible = "fixed-clock"; 111 #clock-cells = <0>; 112 clock-frequency = <25000000>; 113 }; 114 115 arm_timer_clk: arm-timer { 116 #clock-cells = <0>; 117 compatible = "fixed-clock"; 118 clock-frequency = <50000000>; 119 }; 120 }; 121 122 thermal-zones { 123 cpu-thermal { 124 polling-delay-passive = <250>; /* 250ms */ 125 polling-delay = <1000>; /* 1000ms */ 126 thermal-sensors = <&pvtctl>; 127 128 trips { 129 cpu_crit: cpu-crit { 130 temperature = <95000>; /* 95C */ 131 hysteresis = <2000>; 132 type = "critical"; 133 }; 134 cpu_alert: cpu-alert { 135 temperature = <85000>; /* 85C */ 136 hysteresis = <2000>; 137 type = "passive"; 138 }; 139 }; 140 141 cooling-maps { 142 map { 143 trip = <&cpu_alert>; 144 cooling-device = <&cpu0 145 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 146 }; 147 }; 148 }; 149 }; 150 151 soc { 152 compatible = "simple-bus"; 153 #address-cells = <1>; 154 #size-cells = <1>; 155 ranges; 156 interrupt-parent = <&intc>; 157 158 l2: l2-cache@500c0000 { 159 compatible = "socionext,uniphier-system-cache"; 160 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, 161 <0x506c0000 0x400>; 162 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; 163 cache-unified; 164 cache-size = <(1280 * 1024)>; 165 cache-sets = <512>; 166 cache-line-size = <128>; 167 cache-level = <2>; 168 }; 169 170 spi0: spi@54006000 { 171 compatible = "socionext,uniphier-scssi"; 172 status = "disabled"; 173 reg = <0x54006000 0x100>; 174 interrupts = <0 39 4>; 175 pinctrl-names = "default"; 176 pinctrl-0 = <&pinctrl_spi0>; 177 clocks = <&peri_clk 11>; 178 resets = <&peri_rst 11>; 179 }; 180 181 spi1: spi@54006100 { 182 compatible = "socionext,uniphier-scssi"; 183 status = "disabled"; 184 reg = <0x54006100 0x100>; 185 interrupts = <0 216 4>; 186 pinctrl-names = "default"; 187 pinctrl-0 = <&pinctrl_spi1>; 188 clocks = <&peri_clk 11>; 189 resets = <&peri_rst 11>; 190 }; 191 192 serial0: serial@54006800 { 193 compatible = "socionext,uniphier-uart"; 194 status = "disabled"; 195 reg = <0x54006800 0x40>; 196 interrupts = <0 33 4>; 197 pinctrl-names = "default"; 198 pinctrl-0 = <&pinctrl_uart0>; 199 clocks = <&peri_clk 0>; 200 resets = <&peri_rst 0>; 201 }; 202 203 serial1: serial@54006900 { 204 compatible = "socionext,uniphier-uart"; 205 status = "disabled"; 206 reg = <0x54006900 0x40>; 207 interrupts = <0 35 4>; 208 pinctrl-names = "default"; 209 pinctrl-0 = <&pinctrl_uart1>; 210 clocks = <&peri_clk 1>; 211 resets = <&peri_rst 1>; 212 }; 213 214 serial2: serial@54006a00 { 215 compatible = "socionext,uniphier-uart"; 216 status = "disabled"; 217 reg = <0x54006a00 0x40>; 218 interrupts = <0 37 4>; 219 pinctrl-names = "default"; 220 pinctrl-0 = <&pinctrl_uart2>; 221 clocks = <&peri_clk 2>; 222 resets = <&peri_rst 2>; 223 }; 224 225 serial3: serial@54006b00 { 226 compatible = "socionext,uniphier-uart"; 227 status = "disabled"; 228 reg = <0x54006b00 0x40>; 229 interrupts = <0 177 4>; 230 pinctrl-names = "default"; 231 pinctrl-0 = <&pinctrl_uart3>; 232 clocks = <&peri_clk 3>; 233 resets = <&peri_rst 3>; 234 }; 235 236 gpio: gpio@55000000 { 237 compatible = "socionext,uniphier-gpio"; 238 reg = <0x55000000 0x200>; 239 interrupt-parent = <&aidet>; 240 interrupt-controller; 241 #interrupt-cells = <2>; 242 gpio-controller; 243 #gpio-cells = <2>; 244 gpio-ranges = <&pinctrl 0 0 0>, 245 <&pinctrl 96 0 0>; 246 gpio-ranges-group-names = "gpio_range0", 247 "gpio_range1"; 248 ngpios = <232>; 249 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 250 <21 217 3>; 251 }; 252 253 audio@56000000 { 254 compatible = "socionext,uniphier-pxs2-aio"; 255 reg = <0x56000000 0x80000>; 256 interrupts = <0 144 4>; 257 pinctrl-names = "default"; 258 pinctrl-0 = <&pinctrl_ain1>, 259 <&pinctrl_ain2>, 260 <&pinctrl_ainiec1>, 261 <&pinctrl_aout2>, 262 <&pinctrl_aout3>, 263 <&pinctrl_aoutiec1>, 264 <&pinctrl_aoutiec2>; 265 clock-names = "aio"; 266 clocks = <&sys_clk 40>; 267 reset-names = "aio"; 268 resets = <&sys_rst 40>; 269 #sound-dai-cells = <1>; 270 socionext,syscon = <&soc_glue>; 271 272 i2s_port0: port@0 { 273 i2s_hdmi: endpoint { 274 }; 275 }; 276 277 i2s_port1: port@1 { 278 i2s_line: endpoint { 279 }; 280 }; 281 282 i2s_port2: port@2 { 283 i2s_aux: endpoint { 284 }; 285 }; 286 287 spdif_port0: port@3 { 288 spdif_hiecout1: endpoint { 289 }; 290 }; 291 292 spdif_port1: port@4 { 293 spdif_iecout1: endpoint { 294 }; 295 }; 296 297 comp_spdif_port0: port@5 { 298 comp_spdif_hiecout1: endpoint { 299 }; 300 }; 301 302 comp_spdif_port1: port@6 { 303 comp_spdif_iecout1: endpoint { 304 }; 305 }; 306 }; 307 308 i2c0: i2c@58780000 { 309 compatible = "socionext,uniphier-fi2c"; 310 status = "disabled"; 311 reg = <0x58780000 0x80>; 312 #address-cells = <1>; 313 #size-cells = <0>; 314 interrupts = <0 41 4>; 315 pinctrl-names = "default"; 316 pinctrl-0 = <&pinctrl_i2c0>; 317 clocks = <&peri_clk 4>; 318 resets = <&peri_rst 4>; 319 clock-frequency = <100000>; 320 }; 321 322 i2c1: i2c@58781000 { 323 compatible = "socionext,uniphier-fi2c"; 324 status = "disabled"; 325 reg = <0x58781000 0x80>; 326 #address-cells = <1>; 327 #size-cells = <0>; 328 interrupts = <0 42 4>; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&pinctrl_i2c1>; 331 clocks = <&peri_clk 5>; 332 resets = <&peri_rst 5>; 333 clock-frequency = <100000>; 334 }; 335 336 i2c2: i2c@58782000 { 337 compatible = "socionext,uniphier-fi2c"; 338 status = "disabled"; 339 reg = <0x58782000 0x80>; 340 #address-cells = <1>; 341 #size-cells = <0>; 342 interrupts = <0 43 4>; 343 pinctrl-names = "default"; 344 pinctrl-0 = <&pinctrl_i2c2>; 345 clocks = <&peri_clk 6>; 346 resets = <&peri_rst 6>; 347 clock-frequency = <100000>; 348 }; 349 350 i2c3: i2c@58783000 { 351 compatible = "socionext,uniphier-fi2c"; 352 status = "disabled"; 353 reg = <0x58783000 0x80>; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 interrupts = <0 44 4>; 357 pinctrl-names = "default"; 358 pinctrl-0 = <&pinctrl_i2c3>; 359 clocks = <&peri_clk 7>; 360 resets = <&peri_rst 7>; 361 clock-frequency = <100000>; 362 }; 363 364 /* chip-internal connection for DMD */ 365 i2c4: i2c@58784000 { 366 compatible = "socionext,uniphier-fi2c"; 367 reg = <0x58784000 0x80>; 368 #address-cells = <1>; 369 #size-cells = <0>; 370 interrupts = <0 45 4>; 371 clocks = <&peri_clk 8>; 372 resets = <&peri_rst 8>; 373 clock-frequency = <400000>; 374 }; 375 376 /* chip-internal connection for STM */ 377 i2c5: i2c@58785000 { 378 compatible = "socionext,uniphier-fi2c"; 379 reg = <0x58785000 0x80>; 380 #address-cells = <1>; 381 #size-cells = <0>; 382 interrupts = <0 25 4>; 383 clocks = <&peri_clk 9>; 384 resets = <&peri_rst 9>; 385 clock-frequency = <400000>; 386 }; 387 388 /* chip-internal connection for HDMI */ 389 i2c6: i2c@58786000 { 390 compatible = "socionext,uniphier-fi2c"; 391 reg = <0x58786000 0x80>; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 interrupts = <0 26 4>; 395 clocks = <&peri_clk 10>; 396 resets = <&peri_rst 10>; 397 clock-frequency = <400000>; 398 }; 399 400 system_bus: system-bus@58c00000 { 401 compatible = "socionext,uniphier-system-bus"; 402 status = "disabled"; 403 reg = <0x58c00000 0x400>; 404 #address-cells = <2>; 405 #size-cells = <1>; 406 pinctrl-names = "default"; 407 pinctrl-0 = <&pinctrl_system_bus>; 408 }; 409 410 smpctrl@59801000 { 411 compatible = "socionext,uniphier-smpctrl"; 412 reg = <0x59801000 0x400>; 413 }; 414 415 sdctrl@59810000 { 416 compatible = "socionext,uniphier-pxs2-sdctrl", 417 "simple-mfd", "syscon"; 418 reg = <0x59810000 0x400>; 419 420 sd_clk: clock { 421 compatible = "socionext,uniphier-pxs2-sd-clock"; 422 #clock-cells = <1>; 423 }; 424 425 sd_rst: reset { 426 compatible = "socionext,uniphier-pxs2-sd-reset"; 427 #reset-cells = <1>; 428 }; 429 }; 430 431 perictrl@59820000 { 432 compatible = "socionext,uniphier-pxs2-perictrl", 433 "simple-mfd", "syscon"; 434 reg = <0x59820000 0x200>; 435 436 peri_clk: clock { 437 compatible = "socionext,uniphier-pxs2-peri-clock"; 438 #clock-cells = <1>; 439 }; 440 441 peri_rst: reset { 442 compatible = "socionext,uniphier-pxs2-peri-reset"; 443 #reset-cells = <1>; 444 }; 445 }; 446 447 emmc: sdhc@5a000000 { 448 compatible = "socionext,uniphier-sd-v3.1.1"; 449 status = "disabled"; 450 reg = <0x5a000000 0x800>; 451 interrupts = <0 78 4>; 452 pinctrl-names = "default"; 453 pinctrl-0 = <&pinctrl_emmc>; 454 clocks = <&sd_clk 1>; 455 reset-names = "host", "hw"; 456 resets = <&sd_rst 1>, <&sd_rst 6>; 457 bus-width = <8>; 458 cap-mmc-highspeed; 459 cap-mmc-hw-reset; 460 non-removable; 461 }; 462 463 sd: sdhc@5a400000 { 464 compatible = "socionext,uniphier-sd-v3.1.1"; 465 status = "disabled"; 466 reg = <0x5a400000 0x800>; 467 interrupts = <0 76 4>; 468 pinctrl-names = "default", "uhs"; 469 pinctrl-0 = <&pinctrl_sd>; 470 pinctrl-1 = <&pinctrl_sd_uhs>; 471 clocks = <&sd_clk 0>; 472 reset-names = "host"; 473 resets = <&sd_rst 0>; 474 bus-width = <4>; 475 cap-sd-highspeed; 476 sd-uhs-sdr12; 477 sd-uhs-sdr25; 478 sd-uhs-sdr50; 479 }; 480 481 soc_glue: soc-glue@5f800000 { 482 compatible = "socionext,uniphier-pxs2-soc-glue", 483 "simple-mfd", "syscon"; 484 reg = <0x5f800000 0x2000>; 485 486 pinctrl: pinctrl { 487 compatible = "socionext,uniphier-pxs2-pinctrl"; 488 }; 489 }; 490 491 soc-glue@5f900000 { 492 compatible = "socionext,uniphier-pxs2-soc-glue-debug", 493 "simple-mfd"; 494 #address-cells = <1>; 495 #size-cells = <1>; 496 ranges = <0 0x5f900000 0x2000>; 497 498 efuse@100 { 499 compatible = "socionext,uniphier-efuse"; 500 reg = <0x100 0x28>; 501 }; 502 503 efuse@200 { 504 compatible = "socionext,uniphier-efuse"; 505 reg = <0x200 0x58>; 506 }; 507 }; 508 509 aidet: aidet@5fc20000 { 510 compatible = "socionext,uniphier-pxs2-aidet"; 511 reg = <0x5fc20000 0x200>; 512 interrupt-controller; 513 #interrupt-cells = <2>; 514 }; 515 516 timer@60000200 { 517 compatible = "arm,cortex-a9-global-timer"; 518 reg = <0x60000200 0x20>; 519 interrupts = <1 11 0xf04>; 520 clocks = <&arm_timer_clk>; 521 }; 522 523 timer@60000600 { 524 compatible = "arm,cortex-a9-twd-timer"; 525 reg = <0x60000600 0x20>; 526 interrupts = <1 13 0xf04>; 527 clocks = <&arm_timer_clk>; 528 }; 529 530 intc: interrupt-controller@60001000 { 531 compatible = "arm,cortex-a9-gic"; 532 reg = <0x60001000 0x1000>, 533 <0x60000100 0x100>; 534 #interrupt-cells = <3>; 535 interrupt-controller; 536 }; 537 538 sysctrl@61840000 { 539 compatible = "socionext,uniphier-pxs2-sysctrl", 540 "simple-mfd", "syscon"; 541 reg = <0x61840000 0x10000>; 542 543 sys_clk: clock { 544 compatible = "socionext,uniphier-pxs2-clock"; 545 #clock-cells = <1>; 546 }; 547 548 sys_rst: reset { 549 compatible = "socionext,uniphier-pxs2-reset"; 550 #reset-cells = <1>; 551 }; 552 553 pvtctl: pvtctl { 554 compatible = "socionext,uniphier-pxs2-thermal"; 555 interrupts = <0 3 4>; 556 #thermal-sensor-cells = <0>; 557 socionext,tmod-calibration = <0x0f86 0x6844>; 558 }; 559 }; 560 561 eth: ethernet@65000000 { 562 compatible = "socionext,uniphier-pxs2-ave4"; 563 status = "disabled"; 564 reg = <0x65000000 0x8500>; 565 interrupts = <0 66 4>; 566 pinctrl-names = "default"; 567 pinctrl-0 = <&pinctrl_ether_rgmii>; 568 clock-names = "ether"; 569 clocks = <&sys_clk 6>; 570 reset-names = "ether"; 571 resets = <&sys_rst 6>; 572 phy-mode = "rgmii"; 573 local-mac-address = [00 00 00 00 00 00]; 574 socionext,syscon-phy-mode = <&soc_glue 0>; 575 576 mdio: mdio { 577 #address-cells = <1>; 578 #size-cells = <0>; 579 }; 580 }; 581 582 _usb0: usb@65a00000 { 583 compatible = "socionext,uniphier-dwc3", "snps,dwc3"; 584 status = "disabled"; 585 reg = <0x65a00000 0xcd00>; 586 interrupt-names = "host", "peripheral"; 587 interrupts = <0 134 4>, <0 135 4>; 588 pinctrl-names = "default"; 589 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; 590 clock-names = "ref", "bus_early", "suspend"; 591 clocks = <&sys_clk 14>, <&sys_clk 14>, <&sys_clk 14>; 592 resets = <&usb0_rst 15>; 593 phys = <&usb0_hsphy0>, <&usb0_hsphy1>, 594 <&usb0_ssphy0>, <&usb0_ssphy1>; 595 dr_mode = "host"; 596 }; 597 598 usb-glue@65b00000 { 599 compatible = "socionext,uniphier-pxs2-dwc3-glue", 600 "simple-mfd"; 601 #address-cells = <1>; 602 #size-cells = <1>; 603 ranges = <0 0x65b00000 0x400>; 604 605 usb0_rst: reset@0 { 606 compatible = "socionext,uniphier-pxs2-usb3-reset"; 607 reg = <0x0 0x4>; 608 #reset-cells = <1>; 609 clock-names = "link"; 610 clocks = <&sys_clk 14>; 611 reset-names = "link"; 612 resets = <&sys_rst 14>; 613 }; 614 615 usb0_vbus0: regulator@100 { 616 compatible = "socionext,uniphier-pxs2-usb3-regulator"; 617 reg = <0x100 0x10>; 618 clock-names = "link"; 619 clocks = <&sys_clk 14>; 620 reset-names = "link"; 621 resets = <&sys_rst 14>; 622 }; 623 624 usb0_vbus1: regulator@110 { 625 compatible = "socionext,uniphier-pxs2-usb3-regulator"; 626 reg = <0x110 0x10>; 627 clock-names = "link"; 628 clocks = <&sys_clk 14>; 629 reset-names = "link"; 630 resets = <&sys_rst 14>; 631 }; 632 633 usb0_hsphy0: hs-phy@200 { 634 compatible = "socionext,uniphier-pxs2-usb3-hsphy"; 635 reg = <0x200 0x10>; 636 #phy-cells = <0>; 637 clock-names = "link", "phy"; 638 clocks = <&sys_clk 14>, <&sys_clk 16>; 639 reset-names = "link", "phy"; 640 resets = <&sys_rst 14>, <&sys_rst 16>; 641 vbus-supply = <&usb0_vbus0>; 642 }; 643 644 usb0_hsphy1: hs-phy@210 { 645 compatible = "socionext,uniphier-pxs2-usb3-hsphy"; 646 reg = <0x210 0x10>; 647 #phy-cells = <0>; 648 clock-names = "link", "phy"; 649 clocks = <&sys_clk 14>, <&sys_clk 16>; 650 reset-names = "link", "phy"; 651 resets = <&sys_rst 14>, <&sys_rst 16>; 652 vbus-supply = <&usb0_vbus1>; 653 }; 654 655 usb0_ssphy0: ss-phy@300 { 656 compatible = "socionext,uniphier-pxs2-usb3-ssphy"; 657 reg = <0x300 0x10>; 658 #phy-cells = <0>; 659 clock-names = "link", "phy"; 660 clocks = <&sys_clk 14>, <&sys_clk 17>; 661 reset-names = "link", "phy"; 662 resets = <&sys_rst 14>, <&sys_rst 17>; 663 vbus-supply = <&usb0_vbus0>; 664 }; 665 666 usb0_ssphy1: ss-phy@310 { 667 compatible = "socionext,uniphier-pxs2-usb3-ssphy"; 668 reg = <0x310 0x10>; 669 #phy-cells = <0>; 670 clock-names = "link", "phy"; 671 clocks = <&sys_clk 14>, <&sys_clk 18>; 672 reset-names = "link", "phy"; 673 resets = <&sys_rst 14>, <&sys_rst 18>; 674 vbus-supply = <&usb0_vbus1>; 675 }; 676 }; 677 678 /* FIXME: U-Boot own node */ 679 usb0: usb@65b00000 { 680 compatible = "socionext,uniphier-pxs2-dwc3"; 681 status = "disabled"; 682 reg = <0x65b00000 0x1000>; 683 #address-cells = <1>; 684 #size-cells = <1>; 685 ranges; 686 pinctrl-names = "default"; 687 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; 688 dwc3@65a00000 { 689 compatible = "snps,dwc3"; 690 reg = <0x65a00000 0x10000>; 691 interrupts = <0 134 4>; 692 dr_mode = "host"; 693 tx-fifo-resize; 694 }; 695 }; 696 697 _usb1: usb@65c00000 { 698 compatible = "socionext,uniphier-dwc3", "snps,dwc3"; 699 status = "disabled"; 700 reg = <0x65c00000 0xcd00>; 701 interrupt-names = "host", "peripheral"; 702 interrupts = <0 137 4>, <0 138 4>; 703 pinctrl-names = "default"; 704 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; 705 clock-names = "ref", "bus_early", "suspend"; 706 clocks = <&sys_clk 15>, <&sys_clk 15>, <&sys_clk 15>; 707 resets = <&usb1_rst 15>; 708 phys = <&usb1_hsphy0>, <&usb1_hsphy1>, <&usb1_ssphy0>; 709 dr_mode = "host"; 710 }; 711 712 usb-glue@65d00000 { 713 compatible = "socionext,uniphier-pxs2-dwc3-glue", 714 "simple-mfd"; 715 #address-cells = <1>; 716 #size-cells = <1>; 717 ranges = <0 0x65d00000 0x400>; 718 719 usb1_rst: reset@0 { 720 compatible = "socionext,uniphier-pxs2-usb3-reset"; 721 reg = <0x0 0x4>; 722 #reset-cells = <1>; 723 clock-names = "link"; 724 clocks = <&sys_clk 15>; 725 reset-names = "link"; 726 resets = <&sys_rst 15>; 727 }; 728 729 usb1_vbus0: regulator@100 { 730 compatible = "socionext,uniphier-pxs2-usb3-regulator"; 731 reg = <0x100 0x10>; 732 clock-names = "link"; 733 clocks = <&sys_clk 15>; 734 reset-names = "link"; 735 resets = <&sys_rst 15>; 736 }; 737 738 usb1_vbus1: regulator@110 { 739 compatible = "socionext,uniphier-pxs2-usb3-regulator"; 740 reg = <0x110 0x10>; 741 clock-names = "link"; 742 clocks = <&sys_clk 15>; 743 reset-names = "link"; 744 resets = <&sys_rst 15>; 745 }; 746 747 usb1_hsphy0: hs-phy@200 { 748 compatible = "socionext,uniphier-pxs2-usb3-hsphy"; 749 reg = <0x200 0x10>; 750 #phy-cells = <0>; 751 clock-names = "link", "phy"; 752 clocks = <&sys_clk 15>, <&sys_clk 20>; 753 reset-names = "link", "phy"; 754 resets = <&sys_rst 15>, <&sys_rst 20>; 755 vbus-supply = <&usb1_vbus0>; 756 }; 757 758 usb1_hsphy1: hs-phy@210 { 759 compatible = "socionext,uniphier-pxs2-usb3-hsphy"; 760 reg = <0x210 0x10>; 761 #phy-cells = <0>; 762 clock-names = "link", "phy"; 763 clocks = <&sys_clk 15>, <&sys_clk 20>; 764 reset-names = "link", "phy"; 765 resets = <&sys_rst 15>, <&sys_rst 20>; 766 vbus-supply = <&usb1_vbus1>; 767 }; 768 769 usb1_ssphy0: ss-phy@300 { 770 compatible = "socionext,uniphier-pxs2-usb3-ssphy"; 771 reg = <0x300 0x10>; 772 #phy-cells = <0>; 773 clock-names = "link", "phy"; 774 clocks = <&sys_clk 15>, <&sys_clk 21>; 775 reset-names = "link", "phy"; 776 resets = <&sys_rst 15>, <&sys_rst 21>; 777 vbus-supply = <&usb1_vbus0>; 778 }; 779 }; 780 781 /* FIXME: U-Boot own node */ 782 usb1: usb@65d00000 { 783 compatible = "socionext,uniphier-pxs2-dwc3"; 784 status = "disabled"; 785 reg = <0x65d00000 0x1000>; 786 #address-cells = <1>; 787 #size-cells = <1>; 788 ranges; 789 pinctrl-names = "default"; 790 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; 791 dwc3@65c00000 { 792 compatible = "snps,dwc3"; 793 reg = <0x65c00000 0x10000>; 794 interrupts = <0 137 4>; 795 dr_mode = "host"; 796 tx-fifo-resize; 797 }; 798 }; 799 800 nand: nand@68000000 { 801 compatible = "socionext,uniphier-denali-nand-v5b"; 802 status = "disabled"; 803 reg-names = "nand_data", "denali_reg"; 804 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 805 interrupts = <0 65 4>; 806 pinctrl-names = "default"; 807 pinctrl-0 = <&pinctrl_nand2cs>; 808 clock-names = "nand", "nand_x", "ecc"; 809 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; 810 resets = <&sys_rst 2>; 811 }; 812 }; 813}; 814 815#include "uniphier-pinctrl.dtsi" 816