1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Device Tree Source for UniPhier PXs2 SoC 4// 5// Copyright (C) 2015-2016 Socionext Inc. 6// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 8#include <dt-bindings/gpio/uniphier-gpio.h> 9#include <dt-bindings/thermal/thermal.h> 10 11/ { 12 compatible = "socionext,uniphier-pxs2"; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 device_type = "cpu"; 22 compatible = "arm,cortex-a9"; 23 reg = <0>; 24 clocks = <&sys_clk 32>; 25 enable-method = "psci"; 26 next-level-cache = <&l2>; 27 operating-points-v2 = <&cpu_opp>; 28 #cooling-cells = <2>; 29 }; 30 31 cpu1: cpu@1 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a9"; 34 reg = <1>; 35 clocks = <&sys_clk 32>; 36 enable-method = "psci"; 37 next-level-cache = <&l2>; 38 operating-points-v2 = <&cpu_opp>; 39 #cooling-cells = <2>; 40 }; 41 42 cpu2: cpu@2 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a9"; 45 reg = <2>; 46 clocks = <&sys_clk 32>; 47 enable-method = "psci"; 48 next-level-cache = <&l2>; 49 operating-points-v2 = <&cpu_opp>; 50 #cooling-cells = <2>; 51 }; 52 53 cpu3: cpu@3 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a9"; 56 reg = <3>; 57 clocks = <&sys_clk 32>; 58 enable-method = "psci"; 59 next-level-cache = <&l2>; 60 operating-points-v2 = <&cpu_opp>; 61 #cooling-cells = <2>; 62 }; 63 }; 64 65 cpu_opp: opp-table { 66 compatible = "operating-points-v2"; 67 opp-shared; 68 69 opp-100000000 { 70 opp-hz = /bits/ 64 <100000000>; 71 clock-latency-ns = <300>; 72 }; 73 opp-150000000 { 74 opp-hz = /bits/ 64 <150000000>; 75 clock-latency-ns = <300>; 76 }; 77 opp-200000000 { 78 opp-hz = /bits/ 64 <200000000>; 79 clock-latency-ns = <300>; 80 }; 81 opp-300000000 { 82 opp-hz = /bits/ 64 <300000000>; 83 clock-latency-ns = <300>; 84 }; 85 opp-400000000 { 86 opp-hz = /bits/ 64 <400000000>; 87 clock-latency-ns = <300>; 88 }; 89 opp-600000000 { 90 opp-hz = /bits/ 64 <600000000>; 91 clock-latency-ns = <300>; 92 }; 93 opp-800000000 { 94 opp-hz = /bits/ 64 <800000000>; 95 clock-latency-ns = <300>; 96 }; 97 opp-1200000000 { 98 opp-hz = /bits/ 64 <1200000000>; 99 clock-latency-ns = <300>; 100 }; 101 }; 102 103 psci { 104 compatible = "arm,psci-0.2"; 105 method = "smc"; 106 }; 107 108 clocks { 109 refclk: ref { 110 compatible = "fixed-clock"; 111 #clock-cells = <0>; 112 clock-frequency = <25000000>; 113 }; 114 115 arm_timer_clk: arm-timer { 116 #clock-cells = <0>; 117 compatible = "fixed-clock"; 118 clock-frequency = <50000000>; 119 }; 120 }; 121 122 thermal-zones { 123 cpu-thermal { 124 polling-delay-passive = <250>; /* 250ms */ 125 polling-delay = <1000>; /* 1000ms */ 126 thermal-sensors = <&pvtctl>; 127 128 trips { 129 cpu_crit: cpu-crit { 130 temperature = <95000>; /* 95C */ 131 hysteresis = <2000>; 132 type = "critical"; 133 }; 134 cpu_alert: cpu-alert { 135 temperature = <85000>; /* 85C */ 136 hysteresis = <2000>; 137 type = "passive"; 138 }; 139 }; 140 141 cooling-maps { 142 map { 143 trip = <&cpu_alert>; 144 cooling-device = <&cpu0 145 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 146 }; 147 }; 148 }; 149 }; 150 151 soc { 152 compatible = "simple-bus"; 153 #address-cells = <1>; 154 #size-cells = <1>; 155 ranges; 156 interrupt-parent = <&intc>; 157 158 l2: l2-cache@500c0000 { 159 compatible = "socionext,uniphier-system-cache"; 160 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, 161 <0x506c0000 0x400>; 162 interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; 163 cache-unified; 164 cache-size = <(1280 * 1024)>; 165 cache-sets = <512>; 166 cache-line-size = <128>; 167 cache-level = <2>; 168 }; 169 170 serial0: serial@54006800 { 171 compatible = "socionext,uniphier-uart"; 172 status = "disabled"; 173 reg = <0x54006800 0x40>; 174 interrupts = <0 33 4>; 175 pinctrl-names = "default"; 176 pinctrl-0 = <&pinctrl_uart0>; 177 clocks = <&peri_clk 0>; 178 resets = <&peri_rst 0>; 179 }; 180 181 serial1: serial@54006900 { 182 compatible = "socionext,uniphier-uart"; 183 status = "disabled"; 184 reg = <0x54006900 0x40>; 185 interrupts = <0 35 4>; 186 pinctrl-names = "default"; 187 pinctrl-0 = <&pinctrl_uart1>; 188 clocks = <&peri_clk 1>; 189 resets = <&peri_rst 1>; 190 }; 191 192 serial2: serial@54006a00 { 193 compatible = "socionext,uniphier-uart"; 194 status = "disabled"; 195 reg = <0x54006a00 0x40>; 196 interrupts = <0 37 4>; 197 pinctrl-names = "default"; 198 pinctrl-0 = <&pinctrl_uart2>; 199 clocks = <&peri_clk 2>; 200 resets = <&peri_rst 2>; 201 }; 202 203 serial3: serial@54006b00 { 204 compatible = "socionext,uniphier-uart"; 205 status = "disabled"; 206 reg = <0x54006b00 0x40>; 207 interrupts = <0 177 4>; 208 pinctrl-names = "default"; 209 pinctrl-0 = <&pinctrl_uart3>; 210 clocks = <&peri_clk 3>; 211 resets = <&peri_rst 3>; 212 }; 213 214 gpio: gpio@55000000 { 215 compatible = "socionext,uniphier-gpio"; 216 reg = <0x55000000 0x200>; 217 interrupt-parent = <&aidet>; 218 interrupt-controller; 219 #interrupt-cells = <2>; 220 gpio-controller; 221 #gpio-cells = <2>; 222 gpio-ranges = <&pinctrl 0 0 0>, 223 <&pinctrl 96 0 0>; 224 gpio-ranges-group-names = "gpio_range0", 225 "gpio_range1"; 226 ngpios = <232>; 227 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 228 <21 217 3>; 229 }; 230 231 audio@56000000 { 232 compatible = "socionext,uniphier-pxs2-aio"; 233 reg = <0x56000000 0x80000>; 234 interrupts = <0 144 4>; 235 pinctrl-names = "default"; 236 pinctrl-0 = <&pinctrl_ain1>, 237 <&pinctrl_ain2>, 238 <&pinctrl_ainiec1>, 239 <&pinctrl_aout2>, 240 <&pinctrl_aout3>, 241 <&pinctrl_aoutiec1>, 242 <&pinctrl_aoutiec2>; 243 clock-names = "aio"; 244 clocks = <&sys_clk 40>; 245 reset-names = "aio"; 246 resets = <&sys_rst 40>; 247 #sound-dai-cells = <1>; 248 socionext,syscon = <&soc_glue>; 249 250 i2s_port0: port@0 { 251 i2s_hdmi: endpoint { 252 }; 253 }; 254 255 i2s_port1: port@1 { 256 i2s_line: endpoint { 257 }; 258 }; 259 260 i2s_port2: port@2 { 261 i2s_aux: endpoint { 262 }; 263 }; 264 265 spdif_port0: port@3 { 266 spdif_hiecout1: endpoint { 267 }; 268 }; 269 270 spdif_port1: port@4 { 271 spdif_iecout1: endpoint { 272 }; 273 }; 274 275 comp_spdif_port0: port@5 { 276 comp_spdif_hiecout1: endpoint { 277 }; 278 }; 279 280 comp_spdif_port1: port@6 { 281 comp_spdif_iecout1: endpoint { 282 }; 283 }; 284 }; 285 286 i2c0: i2c@58780000 { 287 compatible = "socionext,uniphier-fi2c"; 288 status = "disabled"; 289 reg = <0x58780000 0x80>; 290 #address-cells = <1>; 291 #size-cells = <0>; 292 interrupts = <0 41 4>; 293 pinctrl-names = "default"; 294 pinctrl-0 = <&pinctrl_i2c0>; 295 clocks = <&peri_clk 4>; 296 resets = <&peri_rst 4>; 297 clock-frequency = <100000>; 298 }; 299 300 i2c1: i2c@58781000 { 301 compatible = "socionext,uniphier-fi2c"; 302 status = "disabled"; 303 reg = <0x58781000 0x80>; 304 #address-cells = <1>; 305 #size-cells = <0>; 306 interrupts = <0 42 4>; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&pinctrl_i2c1>; 309 clocks = <&peri_clk 5>; 310 resets = <&peri_rst 5>; 311 clock-frequency = <100000>; 312 }; 313 314 i2c2: i2c@58782000 { 315 compatible = "socionext,uniphier-fi2c"; 316 status = "disabled"; 317 reg = <0x58782000 0x80>; 318 #address-cells = <1>; 319 #size-cells = <0>; 320 interrupts = <0 43 4>; 321 pinctrl-names = "default"; 322 pinctrl-0 = <&pinctrl_i2c2>; 323 clocks = <&peri_clk 6>; 324 resets = <&peri_rst 6>; 325 clock-frequency = <100000>; 326 }; 327 328 i2c3: i2c@58783000 { 329 compatible = "socionext,uniphier-fi2c"; 330 status = "disabled"; 331 reg = <0x58783000 0x80>; 332 #address-cells = <1>; 333 #size-cells = <0>; 334 interrupts = <0 44 4>; 335 pinctrl-names = "default"; 336 pinctrl-0 = <&pinctrl_i2c3>; 337 clocks = <&peri_clk 7>; 338 resets = <&peri_rst 7>; 339 clock-frequency = <100000>; 340 }; 341 342 /* chip-internal connection for DMD */ 343 i2c4: i2c@58784000 { 344 compatible = "socionext,uniphier-fi2c"; 345 reg = <0x58784000 0x80>; 346 #address-cells = <1>; 347 #size-cells = <0>; 348 interrupts = <0 45 4>; 349 clocks = <&peri_clk 8>; 350 resets = <&peri_rst 8>; 351 clock-frequency = <400000>; 352 }; 353 354 /* chip-internal connection for STM */ 355 i2c5: i2c@58785000 { 356 compatible = "socionext,uniphier-fi2c"; 357 reg = <0x58785000 0x80>; 358 #address-cells = <1>; 359 #size-cells = <0>; 360 interrupts = <0 25 4>; 361 clocks = <&peri_clk 9>; 362 resets = <&peri_rst 9>; 363 clock-frequency = <400000>; 364 }; 365 366 /* chip-internal connection for HDMI */ 367 i2c6: i2c@58786000 { 368 compatible = "socionext,uniphier-fi2c"; 369 reg = <0x58786000 0x80>; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 interrupts = <0 26 4>; 373 clocks = <&peri_clk 10>; 374 resets = <&peri_rst 10>; 375 clock-frequency = <400000>; 376 }; 377 378 system_bus: system-bus@58c00000 { 379 compatible = "socionext,uniphier-system-bus"; 380 status = "disabled"; 381 reg = <0x58c00000 0x400>; 382 #address-cells = <2>; 383 #size-cells = <1>; 384 pinctrl-names = "default"; 385 pinctrl-0 = <&pinctrl_system_bus>; 386 }; 387 388 smpctrl@59801000 { 389 compatible = "socionext,uniphier-smpctrl"; 390 reg = <0x59801000 0x400>; 391 }; 392 393 sdctrl@59810000 { 394 compatible = "socionext,uniphier-pxs2-sdctrl", 395 "simple-mfd", "syscon"; 396 reg = <0x59810000 0x400>; 397 398 sd_clk: clock { 399 compatible = "socionext,uniphier-pxs2-sd-clock"; 400 #clock-cells = <1>; 401 }; 402 403 sd_rst: reset { 404 compatible = "socionext,uniphier-pxs2-sd-reset"; 405 #reset-cells = <1>; 406 }; 407 }; 408 409 perictrl@59820000 { 410 compatible = "socionext,uniphier-pxs2-perictrl", 411 "simple-mfd", "syscon"; 412 reg = <0x59820000 0x200>; 413 414 peri_clk: clock { 415 compatible = "socionext,uniphier-pxs2-peri-clock"; 416 #clock-cells = <1>; 417 }; 418 419 peri_rst: reset { 420 compatible = "socionext,uniphier-pxs2-peri-reset"; 421 #reset-cells = <1>; 422 }; 423 }; 424 425 emmc: sdhc@5a000000 { 426 compatible = "socionext,uniphier-sd-v3.1.1"; 427 status = "disabled"; 428 reg = <0x5a000000 0x800>; 429 interrupts = <0 78 4>; 430 pinctrl-names = "default"; 431 pinctrl-0 = <&pinctrl_emmc>; 432 clocks = <&sd_clk 1>; 433 reset-names = "host", "hw"; 434 resets = <&sd_rst 1>, <&sd_rst 6>; 435 bus-width = <8>; 436 cap-mmc-highspeed; 437 cap-mmc-hw-reset; 438 non-removable; 439 }; 440 441 sd: sdhc@5a400000 { 442 compatible = "socionext,uniphier-sd-v3.1.1"; 443 status = "disabled"; 444 reg = <0x5a400000 0x800>; 445 interrupts = <0 76 4>; 446 pinctrl-names = "default", "uhs"; 447 pinctrl-0 = <&pinctrl_sd>; 448 pinctrl-1 = <&pinctrl_sd_uhs>; 449 clocks = <&sd_clk 0>; 450 reset-names = "host"; 451 resets = <&sd_rst 0>; 452 bus-width = <4>; 453 cap-sd-highspeed; 454 sd-uhs-sdr12; 455 sd-uhs-sdr25; 456 sd-uhs-sdr50; 457 }; 458 459 soc_glue: soc-glue@5f800000 { 460 compatible = "socionext,uniphier-pxs2-soc-glue", 461 "simple-mfd", "syscon"; 462 reg = <0x5f800000 0x2000>; 463 464 pinctrl: pinctrl { 465 compatible = "socionext,uniphier-pxs2-pinctrl"; 466 }; 467 }; 468 469 soc-glue@5f900000 { 470 compatible = "socionext,uniphier-pxs2-soc-glue-debug", 471 "simple-mfd"; 472 #address-cells = <1>; 473 #size-cells = <1>; 474 ranges = <0 0x5f900000 0x2000>; 475 476 efuse@100 { 477 compatible = "socionext,uniphier-efuse"; 478 reg = <0x100 0x28>; 479 }; 480 481 efuse@200 { 482 compatible = "socionext,uniphier-efuse"; 483 reg = <0x200 0x58>; 484 }; 485 }; 486 487 aidet: aidet@5fc20000 { 488 compatible = "socionext,uniphier-pxs2-aidet"; 489 reg = <0x5fc20000 0x200>; 490 interrupt-controller; 491 #interrupt-cells = <2>; 492 }; 493 494 timer@60000200 { 495 compatible = "arm,cortex-a9-global-timer"; 496 reg = <0x60000200 0x20>; 497 interrupts = <1 11 0xf04>; 498 clocks = <&arm_timer_clk>; 499 }; 500 501 timer@60000600 { 502 compatible = "arm,cortex-a9-twd-timer"; 503 reg = <0x60000600 0x20>; 504 interrupts = <1 13 0xf04>; 505 clocks = <&arm_timer_clk>; 506 }; 507 508 intc: interrupt-controller@60001000 { 509 compatible = "arm,cortex-a9-gic"; 510 reg = <0x60001000 0x1000>, 511 <0x60000100 0x100>; 512 #interrupt-cells = <3>; 513 interrupt-controller; 514 }; 515 516 sysctrl@61840000 { 517 compatible = "socionext,uniphier-pxs2-sysctrl", 518 "simple-mfd", "syscon"; 519 reg = <0x61840000 0x10000>; 520 521 sys_clk: clock { 522 compatible = "socionext,uniphier-pxs2-clock"; 523 #clock-cells = <1>; 524 }; 525 526 sys_rst: reset { 527 compatible = "socionext,uniphier-pxs2-reset"; 528 #reset-cells = <1>; 529 }; 530 531 pvtctl: pvtctl { 532 compatible = "socionext,uniphier-pxs2-thermal"; 533 interrupts = <0 3 4>; 534 #thermal-sensor-cells = <0>; 535 socionext,tmod-calibration = <0x0f86 0x6844>; 536 }; 537 }; 538 539 eth: ethernet@65000000 { 540 compatible = "socionext,uniphier-pxs2-ave4"; 541 status = "disabled"; 542 reg = <0x65000000 0x8500>; 543 interrupts = <0 66 4>; 544 pinctrl-names = "default"; 545 pinctrl-0 = <&pinctrl_ether_rgmii>; 546 clock-names = "ether"; 547 clocks = <&sys_clk 6>; 548 reset-names = "ether"; 549 resets = <&sys_rst 6>; 550 phy-mode = "rgmii"; 551 local-mac-address = [00 00 00 00 00 00]; 552 socionext,syscon-phy-mode = <&soc_glue 0>; 553 554 mdio: mdio { 555 #address-cells = <1>; 556 #size-cells = <0>; 557 }; 558 }; 559 560 usb0: usb@65b00000 { 561 compatible = "socionext,uniphier-pxs2-dwc3"; 562 status = "disabled"; 563 reg = <0x65b00000 0x1000>; 564 #address-cells = <1>; 565 #size-cells = <1>; 566 ranges; 567 pinctrl-names = "default"; 568 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; 569 dwc3@65a00000 { 570 compatible = "snps,dwc3"; 571 reg = <0x65a00000 0x10000>; 572 interrupts = <0 134 4>; 573 dr_mode = "host"; 574 tx-fifo-resize; 575 }; 576 }; 577 578 usb1: usb@65d00000 { 579 compatible = "socionext,uniphier-pxs2-dwc3"; 580 status = "disabled"; 581 reg = <0x65d00000 0x1000>; 582 #address-cells = <1>; 583 #size-cells = <1>; 584 ranges; 585 pinctrl-names = "default"; 586 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; 587 dwc3@65c00000 { 588 compatible = "snps,dwc3"; 589 reg = <0x65c00000 0x10000>; 590 interrupts = <0 137 4>; 591 dr_mode = "host"; 592 tx-fifo-resize; 593 }; 594 }; 595 596 nand: nand@68000000 { 597 compatible = "socionext,uniphier-denali-nand-v5b"; 598 status = "disabled"; 599 reg-names = "nand_data", "denali_reg"; 600 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 601 interrupts = <0 65 4>; 602 pinctrl-names = "default"; 603 pinctrl-0 = <&pinctrl_nand2cs>; 604 clocks = <&sys_clk 2>; 605 resets = <&sys_rst 2>; 606 }; 607 }; 608}; 609 610#include "uniphier-pinctrl.dtsi" 611