1/* 2 * Device Tree Source for UniPhier Pro5 SoC 3 * 4 * Copyright (C) 2015-2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 */ 9 10/ { 11 compatible = "socionext,uniphier-pro5"; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu@0 { 20 device_type = "cpu"; 21 compatible = "arm,cortex-a9"; 22 reg = <0>; 23 clocks = <&sys_clk 32>; 24 enable-method = "psci"; 25 next-level-cache = <&l2>; 26 operating-points-v2 = <&cpu_opp>; 27 }; 28 29 cpu@1 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a9"; 32 reg = <1>; 33 clocks = <&sys_clk 32>; 34 enable-method = "psci"; 35 next-level-cache = <&l2>; 36 operating-points-v2 = <&cpu_opp>; 37 }; 38 }; 39 40 cpu_opp: opp_table { 41 compatible = "operating-points-v2"; 42 opp-shared; 43 44 opp-100000000 { 45 opp-hz = /bits/ 64 <100000000>; 46 clock-latency-ns = <300>; 47 }; 48 opp-116667000 { 49 opp-hz = /bits/ 64 <116667000>; 50 clock-latency-ns = <300>; 51 }; 52 opp-150000000 { 53 opp-hz = /bits/ 64 <150000000>; 54 clock-latency-ns = <300>; 55 }; 56 opp-175000000 { 57 opp-hz = /bits/ 64 <175000000>; 58 clock-latency-ns = <300>; 59 }; 60 opp-200000000 { 61 opp-hz = /bits/ 64 <200000000>; 62 clock-latency-ns = <300>; 63 }; 64 opp-233334000 { 65 opp-hz = /bits/ 64 <233334000>; 66 clock-latency-ns = <300>; 67 }; 68 opp-300000000 { 69 opp-hz = /bits/ 64 <300000000>; 70 clock-latency-ns = <300>; 71 }; 72 opp-350000000 { 73 opp-hz = /bits/ 64 <350000000>; 74 clock-latency-ns = <300>; 75 }; 76 opp-400000000 { 77 opp-hz = /bits/ 64 <400000000>; 78 clock-latency-ns = <300>; 79 }; 80 opp-466667000 { 81 opp-hz = /bits/ 64 <466667000>; 82 clock-latency-ns = <300>; 83 }; 84 opp-600000000 { 85 opp-hz = /bits/ 64 <600000000>; 86 clock-latency-ns = <300>; 87 }; 88 opp-700000000 { 89 opp-hz = /bits/ 64 <700000000>; 90 clock-latency-ns = <300>; 91 }; 92 opp-800000000 { 93 opp-hz = /bits/ 64 <800000000>; 94 clock-latency-ns = <300>; 95 }; 96 opp-933334000 { 97 opp-hz = /bits/ 64 <933334000>; 98 clock-latency-ns = <300>; 99 }; 100 opp-1200000000 { 101 opp-hz = /bits/ 64 <1200000000>; 102 clock-latency-ns = <300>; 103 }; 104 opp-1400000000 { 105 opp-hz = /bits/ 64 <1400000000>; 106 clock-latency-ns = <300>; 107 }; 108 }; 109 110 psci { 111 compatible = "arm,psci-0.2"; 112 method = "smc"; 113 }; 114 115 clocks { 116 refclk: ref { 117 compatible = "fixed-clock"; 118 #clock-cells = <0>; 119 clock-frequency = <20000000>; 120 }; 121 122 arm_timer_clk: arm_timer_clk { 123 #clock-cells = <0>; 124 compatible = "fixed-clock"; 125 clock-frequency = <50000000>; 126 }; 127 }; 128 129 soc { 130 compatible = "simple-bus"; 131 #address-cells = <1>; 132 #size-cells = <1>; 133 ranges; 134 interrupt-parent = <&intc>; 135 136 l2: l2-cache@500c0000 { 137 compatible = "socionext,uniphier-system-cache"; 138 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, 139 <0x506c0000 0x400>; 140 interrupts = <0 190 4>, <0 191 4>; 141 cache-unified; 142 cache-size = <(2 * 1024 * 1024)>; 143 cache-sets = <512>; 144 cache-line-size = <128>; 145 cache-level = <2>; 146 next-level-cache = <&l3>; 147 }; 148 149 l3: l3-cache@500c8000 { 150 compatible = "socionext,uniphier-system-cache"; 151 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, 152 <0x506c8000 0x400>; 153 interrupts = <0 174 4>, <0 175 4>; 154 cache-unified; 155 cache-size = <(2 * 1024 * 1024)>; 156 cache-sets = <512>; 157 cache-line-size = <256>; 158 cache-level = <3>; 159 }; 160 161 serial0: serial@54006800 { 162 compatible = "socionext,uniphier-uart"; 163 status = "disabled"; 164 reg = <0x54006800 0x40>; 165 interrupts = <0 33 4>; 166 pinctrl-names = "default"; 167 pinctrl-0 = <&pinctrl_uart0>; 168 clocks = <&peri_clk 0>; 169 clock-frequency = <73728000>; 170 }; 171 172 serial1: serial@54006900 { 173 compatible = "socionext,uniphier-uart"; 174 status = "disabled"; 175 reg = <0x54006900 0x40>; 176 interrupts = <0 35 4>; 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_uart1>; 179 clocks = <&peri_clk 1>; 180 clock-frequency = <73728000>; 181 }; 182 183 serial2: serial@54006a00 { 184 compatible = "socionext,uniphier-uart"; 185 status = "disabled"; 186 reg = <0x54006a00 0x40>; 187 interrupts = <0 37 4>; 188 pinctrl-names = "default"; 189 pinctrl-0 = <&pinctrl_uart2>; 190 clocks = <&peri_clk 2>; 191 clock-frequency = <73728000>; 192 }; 193 194 serial3: serial@54006b00 { 195 compatible = "socionext,uniphier-uart"; 196 status = "disabled"; 197 reg = <0x54006b00 0x40>; 198 interrupts = <0 177 4>; 199 pinctrl-names = "default"; 200 pinctrl-0 = <&pinctrl_uart3>; 201 clocks = <&peri_clk 3>; 202 clock-frequency = <73728000>; 203 }; 204 205 gpio: gpio@55000000 { 206 compatible = "socionext,uniphier-gpio"; 207 reg = <0x55000000 0x200>; 208 interrupt-parent = <&aidet>; 209 interrupt-controller; 210 #interrupt-cells = <2>; 211 gpio-controller; 212 #gpio-cells = <2>; 213 gpio-ranges = <&pinctrl 0 0 0>; 214 gpio-ranges-group-names = "gpio_range"; 215 ngpios = <248>; 216 }; 217 218 i2c0: i2c@58780000 { 219 compatible = "socionext,uniphier-fi2c"; 220 status = "disabled"; 221 reg = <0x58780000 0x80>; 222 #address-cells = <1>; 223 #size-cells = <0>; 224 interrupts = <0 41 4>; 225 pinctrl-names = "default"; 226 pinctrl-0 = <&pinctrl_i2c0>; 227 clocks = <&peri_clk 4>; 228 clock-frequency = <100000>; 229 }; 230 231 i2c1: i2c@58781000 { 232 compatible = "socionext,uniphier-fi2c"; 233 status = "disabled"; 234 reg = <0x58781000 0x80>; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 interrupts = <0 42 4>; 238 pinctrl-names = "default"; 239 pinctrl-0 = <&pinctrl_i2c1>; 240 clocks = <&peri_clk 5>; 241 clock-frequency = <100000>; 242 }; 243 244 i2c2: i2c@58782000 { 245 compatible = "socionext,uniphier-fi2c"; 246 status = "disabled"; 247 reg = <0x58782000 0x80>; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 interrupts = <0 43 4>; 251 pinctrl-names = "default"; 252 pinctrl-0 = <&pinctrl_i2c2>; 253 clocks = <&peri_clk 6>; 254 clock-frequency = <100000>; 255 }; 256 257 i2c3: i2c@58783000 { 258 compatible = "socionext,uniphier-fi2c"; 259 status = "disabled"; 260 reg = <0x58783000 0x80>; 261 #address-cells = <1>; 262 #size-cells = <0>; 263 interrupts = <0 44 4>; 264 pinctrl-names = "default"; 265 pinctrl-0 = <&pinctrl_i2c3>; 266 clocks = <&peri_clk 7>; 267 clock-frequency = <100000>; 268 }; 269 270 /* i2c4 does not exist */ 271 272 /* chip-internal connection for DMD */ 273 i2c5: i2c@58785000 { 274 compatible = "socionext,uniphier-fi2c"; 275 reg = <0x58785000 0x80>; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 interrupts = <0 25 4>; 279 clocks = <&peri_clk 9>; 280 clock-frequency = <400000>; 281 }; 282 283 /* chip-internal connection for HDMI */ 284 i2c6: i2c@58786000 { 285 compatible = "socionext,uniphier-fi2c"; 286 reg = <0x58786000 0x80>; 287 #address-cells = <1>; 288 #size-cells = <0>; 289 interrupts = <0 26 4>; 290 clocks = <&peri_clk 10>; 291 clock-frequency = <400000>; 292 }; 293 294 system_bus: system-bus@58c00000 { 295 compatible = "socionext,uniphier-system-bus"; 296 status = "disabled"; 297 reg = <0x58c00000 0x400>; 298 #address-cells = <2>; 299 #size-cells = <1>; 300 pinctrl-names = "default"; 301 pinctrl-0 = <&pinctrl_system_bus>; 302 }; 303 304 smpctrl@59801000 { 305 compatible = "socionext,uniphier-smpctrl"; 306 reg = <0x59801000 0x400>; 307 }; 308 309 sdctrl@59810000 { 310 compatible = "socionext,uniphier-pro5-sdctrl", 311 "simple-mfd", "syscon"; 312 reg = <0x59810000 0x400>; 313 314 sd_clk: clock { 315 compatible = "socionext,uniphier-pro5-sd-clock"; 316 #clock-cells = <1>; 317 }; 318 319 sd_rst: reset { 320 compatible = "socionext,uniphier-pro5-sd-reset"; 321 #reset-cells = <1>; 322 }; 323 }; 324 325 perictrl@59820000 { 326 compatible = "socionext,uniphier-pro5-perictrl", 327 "simple-mfd", "syscon"; 328 reg = <0x59820000 0x200>; 329 330 peri_clk: clock { 331 compatible = "socionext,uniphier-pro5-peri-clock"; 332 #clock-cells = <1>; 333 }; 334 335 peri_rst: reset { 336 compatible = "socionext,uniphier-pro5-peri-reset"; 337 #reset-cells = <1>; 338 }; 339 }; 340 341 soc-glue@5f800000 { 342 compatible = "socionext,uniphier-pro5-soc-glue", 343 "simple-mfd", "syscon"; 344 reg = <0x5f800000 0x2000>; 345 346 pinctrl: pinctrl { 347 compatible = "socionext,uniphier-pro5-pinctrl"; 348 }; 349 }; 350 351 aidet: aidet@5fc20000 { 352 compatible = "socionext,uniphier-pro5-aidet"; 353 reg = <0x5fc20000 0x200>; 354 interrupt-controller; 355 #interrupt-cells = <2>; 356 }; 357 358 timer@60000200 { 359 compatible = "arm,cortex-a9-global-timer"; 360 reg = <0x60000200 0x20>; 361 interrupts = <1 11 0x304>; 362 clocks = <&arm_timer_clk>; 363 }; 364 365 timer@60000600 { 366 compatible = "arm,cortex-a9-twd-timer"; 367 reg = <0x60000600 0x20>; 368 interrupts = <1 13 0x304>; 369 clocks = <&arm_timer_clk>; 370 }; 371 372 intc: interrupt-controller@60001000 { 373 compatible = "arm,cortex-a9-gic"; 374 reg = <0x60001000 0x1000>, 375 <0x60000100 0x100>; 376 #interrupt-cells = <3>; 377 interrupt-controller; 378 }; 379 380 sysctrl@61840000 { 381 compatible = "socionext,uniphier-pro5-sysctrl", 382 "simple-mfd", "syscon"; 383 reg = <0x61840000 0x10000>; 384 385 sys_clk: clock { 386 compatible = "socionext,uniphier-pro5-clock"; 387 #clock-cells = <1>; 388 }; 389 390 sys_rst: reset { 391 compatible = "socionext,uniphier-pro5-reset"; 392 #reset-cells = <1>; 393 }; 394 }; 395 396 usb0: usb@65b00000 { 397 compatible = "socionext,uniphier-pro5-dwc3"; 398 status = "disabled"; 399 reg = <0x65b00000 0x1000>; 400 #address-cells = <1>; 401 #size-cells = <1>; 402 ranges; 403 pinctrl-names = "default"; 404 pinctrl-0 = <&pinctrl_usb0>; 405 dwc3@65a00000 { 406 compatible = "snps,dwc3"; 407 reg = <0x65a00000 0x10000>; 408 interrupts = <0 134 4>; 409 dr_mode = "host"; 410 tx-fifo-resize; 411 }; 412 }; 413 414 usb1: usb@65d00000 { 415 compatible = "socionext,uniphier-pro5-dwc3"; 416 status = "disabled"; 417 reg = <0x65d00000 0x1000>; 418 #address-cells = <1>; 419 #size-cells = <1>; 420 ranges; 421 pinctrl-names = "default"; 422 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>; 423 dwc3@65c00000 { 424 compatible = "snps,dwc3"; 425 reg = <0x65c00000 0x10000>; 426 interrupts = <0 137 4>; 427 dr_mode = "host"; 428 tx-fifo-resize; 429 }; 430 }; 431 432 nand: nand@68000000 { 433 compatible = "socionext,uniphier-denali-nand-v5b"; 434 status = "disabled"; 435 reg-names = "nand_data", "denali_reg"; 436 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 437 interrupts = <0 65 4>; 438 pinctrl-names = "default"; 439 pinctrl-0 = <&pinctrl_nand2cs>; 440 clocks = <&sys_clk 2>; 441 }; 442 443 emmc: sdhc@68400000 { 444 compatible = "socionext,uniphier-sdhc"; 445 status = "disabled"; 446 reg = <0x68400000 0x800>; 447 interrupts = <0 78 4>; 448 pinctrl-names = "default"; 449 pinctrl-0 = <&pinctrl_emmc>; 450 clocks = <&sd_clk 1>; 451 reset-names = "host"; 452 resets = <&sd_rst 1>; 453 bus-width = <8>; 454 non-removable; 455 cap-mmc-highspeed; 456 cap-mmc-hw-reset; 457 no-3-3-v; 458 }; 459 460 sd: sdhc@68800000 { 461 compatible = "socionext,uniphier-sdhc"; 462 status = "disabled"; 463 reg = <0x68800000 0x800>; 464 interrupts = <0 76 4>; 465 pinctrl-names = "default", "1.8v"; 466 pinctrl-0 = <&pinctrl_sd>; 467 pinctrl-1 = <&pinctrl_sd_1v8>; 468 clocks = <&sd_clk 0>; 469 reset-names = "host"; 470 resets = <&sd_rst 0>; 471 bus-width = <4>; 472 cap-sd-highspeed; 473 sd-uhs-sdr12; 474 sd-uhs-sdr25; 475 sd-uhs-sdr50; 476 }; 477 }; 478}; 479 480#include "uniphier-pinctrl.dtsi" 481