1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Device Tree Source for UniPhier Pro5 SoC 4// 5// Copyright (C) 2015-2016 Socionext Inc. 6// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 8/ { 9 compatible = "socionext,uniphier-pro5"; 10 #address-cells = <1>; 11 #size-cells = <1>; 12 13 cpus { 14 #address-cells = <1>; 15 #size-cells = <0>; 16 17 cpu@0 { 18 device_type = "cpu"; 19 compatible = "arm,cortex-a9"; 20 reg = <0>; 21 clocks = <&sys_clk 32>; 22 enable-method = "psci"; 23 next-level-cache = <&l2>; 24 operating-points-v2 = <&cpu_opp>; 25 }; 26 27 cpu@1 { 28 device_type = "cpu"; 29 compatible = "arm,cortex-a9"; 30 reg = <1>; 31 clocks = <&sys_clk 32>; 32 enable-method = "psci"; 33 next-level-cache = <&l2>; 34 operating-points-v2 = <&cpu_opp>; 35 }; 36 }; 37 38 cpu_opp: opp-table { 39 compatible = "operating-points-v2"; 40 opp-shared; 41 42 opp-100000000 { 43 opp-hz = /bits/ 64 <100000000>; 44 clock-latency-ns = <300>; 45 }; 46 opp-116667000 { 47 opp-hz = /bits/ 64 <116667000>; 48 clock-latency-ns = <300>; 49 }; 50 opp-150000000 { 51 opp-hz = /bits/ 64 <150000000>; 52 clock-latency-ns = <300>; 53 }; 54 opp-175000000 { 55 opp-hz = /bits/ 64 <175000000>; 56 clock-latency-ns = <300>; 57 }; 58 opp-200000000 { 59 opp-hz = /bits/ 64 <200000000>; 60 clock-latency-ns = <300>; 61 }; 62 opp-233334000 { 63 opp-hz = /bits/ 64 <233334000>; 64 clock-latency-ns = <300>; 65 }; 66 opp-300000000 { 67 opp-hz = /bits/ 64 <300000000>; 68 clock-latency-ns = <300>; 69 }; 70 opp-350000000 { 71 opp-hz = /bits/ 64 <350000000>; 72 clock-latency-ns = <300>; 73 }; 74 opp-400000000 { 75 opp-hz = /bits/ 64 <400000000>; 76 clock-latency-ns = <300>; 77 }; 78 opp-466667000 { 79 opp-hz = /bits/ 64 <466667000>; 80 clock-latency-ns = <300>; 81 }; 82 opp-600000000 { 83 opp-hz = /bits/ 64 <600000000>; 84 clock-latency-ns = <300>; 85 }; 86 opp-700000000 { 87 opp-hz = /bits/ 64 <700000000>; 88 clock-latency-ns = <300>; 89 }; 90 opp-800000000 { 91 opp-hz = /bits/ 64 <800000000>; 92 clock-latency-ns = <300>; 93 }; 94 opp-933334000 { 95 opp-hz = /bits/ 64 <933334000>; 96 clock-latency-ns = <300>; 97 }; 98 opp-1200000000 { 99 opp-hz = /bits/ 64 <1200000000>; 100 clock-latency-ns = <300>; 101 }; 102 opp-1400000000 { 103 opp-hz = /bits/ 64 <1400000000>; 104 clock-latency-ns = <300>; 105 }; 106 }; 107 108 psci { 109 compatible = "arm,psci-0.2"; 110 method = "smc"; 111 }; 112 113 clocks { 114 refclk: ref { 115 compatible = "fixed-clock"; 116 #clock-cells = <0>; 117 clock-frequency = <20000000>; 118 }; 119 120 arm_timer_clk: arm-timer { 121 #clock-cells = <0>; 122 compatible = "fixed-clock"; 123 clock-frequency = <50000000>; 124 }; 125 }; 126 127 soc { 128 compatible = "simple-bus"; 129 #address-cells = <1>; 130 #size-cells = <1>; 131 ranges; 132 interrupt-parent = <&intc>; 133 134 l2: l2-cache@500c0000 { 135 compatible = "socionext,uniphier-system-cache"; 136 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, 137 <0x506c0000 0x400>; 138 interrupts = <0 190 4>, <0 191 4>; 139 cache-unified; 140 cache-size = <(2 * 1024 * 1024)>; 141 cache-sets = <512>; 142 cache-line-size = <128>; 143 cache-level = <2>; 144 next-level-cache = <&l3>; 145 }; 146 147 l3: l3-cache@500c8000 { 148 compatible = "socionext,uniphier-system-cache"; 149 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, 150 <0x506c8000 0x400>; 151 interrupts = <0 174 4>, <0 175 4>; 152 cache-unified; 153 cache-size = <(2 * 1024 * 1024)>; 154 cache-sets = <512>; 155 cache-line-size = <256>; 156 cache-level = <3>; 157 }; 158 159 serial0: serial@54006800 { 160 compatible = "socionext,uniphier-uart"; 161 status = "disabled"; 162 reg = <0x54006800 0x40>; 163 interrupts = <0 33 4>; 164 pinctrl-names = "default"; 165 pinctrl-0 = <&pinctrl_uart0>; 166 clocks = <&peri_clk 0>; 167 clock-frequency = <73728000>; 168 resets = <&peri_rst 0>; 169 }; 170 171 serial1: serial@54006900 { 172 compatible = "socionext,uniphier-uart"; 173 status = "disabled"; 174 reg = <0x54006900 0x40>; 175 interrupts = <0 35 4>; 176 pinctrl-names = "default"; 177 pinctrl-0 = <&pinctrl_uart1>; 178 clocks = <&peri_clk 1>; 179 clock-frequency = <73728000>; 180 resets = <&peri_rst 1>; 181 }; 182 183 serial2: serial@54006a00 { 184 compatible = "socionext,uniphier-uart"; 185 status = "disabled"; 186 reg = <0x54006a00 0x40>; 187 interrupts = <0 37 4>; 188 pinctrl-names = "default"; 189 pinctrl-0 = <&pinctrl_uart2>; 190 clocks = <&peri_clk 2>; 191 clock-frequency = <73728000>; 192 resets = <&peri_rst 2>; 193 }; 194 195 serial3: serial@54006b00 { 196 compatible = "socionext,uniphier-uart"; 197 status = "disabled"; 198 reg = <0x54006b00 0x40>; 199 interrupts = <0 177 4>; 200 pinctrl-names = "default"; 201 pinctrl-0 = <&pinctrl_uart3>; 202 clocks = <&peri_clk 3>; 203 clock-frequency = <73728000>; 204 resets = <&peri_rst 3>; 205 }; 206 207 gpio: gpio@55000000 { 208 compatible = "socionext,uniphier-gpio"; 209 reg = <0x55000000 0x200>; 210 interrupt-parent = <&aidet>; 211 interrupt-controller; 212 #interrupt-cells = <2>; 213 gpio-controller; 214 #gpio-cells = <2>; 215 gpio-ranges = <&pinctrl 0 0 0>; 216 gpio-ranges-group-names = "gpio_range"; 217 ngpios = <248>; 218 socionext,interrupt-ranges = <0 48 16>, <16 154 5>; 219 }; 220 221 i2c0: i2c@58780000 { 222 compatible = "socionext,uniphier-fi2c"; 223 status = "disabled"; 224 reg = <0x58780000 0x80>; 225 #address-cells = <1>; 226 #size-cells = <0>; 227 interrupts = <0 41 4>; 228 pinctrl-names = "default"; 229 pinctrl-0 = <&pinctrl_i2c0>; 230 clocks = <&peri_clk 4>; 231 resets = <&peri_rst 4>; 232 clock-frequency = <100000>; 233 }; 234 235 i2c1: i2c@58781000 { 236 compatible = "socionext,uniphier-fi2c"; 237 status = "disabled"; 238 reg = <0x58781000 0x80>; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 interrupts = <0 42 4>; 242 pinctrl-names = "default"; 243 pinctrl-0 = <&pinctrl_i2c1>; 244 clocks = <&peri_clk 5>; 245 resets = <&peri_rst 5>; 246 clock-frequency = <100000>; 247 }; 248 249 i2c2: i2c@58782000 { 250 compatible = "socionext,uniphier-fi2c"; 251 status = "disabled"; 252 reg = <0x58782000 0x80>; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 interrupts = <0 43 4>; 256 pinctrl-names = "default"; 257 pinctrl-0 = <&pinctrl_i2c2>; 258 clocks = <&peri_clk 6>; 259 resets = <&peri_rst 6>; 260 clock-frequency = <100000>; 261 }; 262 263 i2c3: i2c@58783000 { 264 compatible = "socionext,uniphier-fi2c"; 265 status = "disabled"; 266 reg = <0x58783000 0x80>; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 interrupts = <0 44 4>; 270 pinctrl-names = "default"; 271 pinctrl-0 = <&pinctrl_i2c3>; 272 clocks = <&peri_clk 7>; 273 resets = <&peri_rst 7>; 274 clock-frequency = <100000>; 275 }; 276 277 /* i2c4 does not exist */ 278 279 /* chip-internal connection for DMD */ 280 i2c5: i2c@58785000 { 281 compatible = "socionext,uniphier-fi2c"; 282 reg = <0x58785000 0x80>; 283 #address-cells = <1>; 284 #size-cells = <0>; 285 interrupts = <0 25 4>; 286 clocks = <&peri_clk 9>; 287 resets = <&peri_rst 9>; 288 clock-frequency = <400000>; 289 }; 290 291 /* chip-internal connection for HDMI */ 292 i2c6: i2c@58786000 { 293 compatible = "socionext,uniphier-fi2c"; 294 reg = <0x58786000 0x80>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 interrupts = <0 26 4>; 298 clocks = <&peri_clk 10>; 299 resets = <&peri_rst 10>; 300 clock-frequency = <400000>; 301 }; 302 303 system_bus: system-bus@58c00000 { 304 compatible = "socionext,uniphier-system-bus"; 305 status = "disabled"; 306 reg = <0x58c00000 0x400>; 307 #address-cells = <2>; 308 #size-cells = <1>; 309 pinctrl-names = "default"; 310 pinctrl-0 = <&pinctrl_system_bus>; 311 }; 312 313 smpctrl@59801000 { 314 compatible = "socionext,uniphier-smpctrl"; 315 reg = <0x59801000 0x400>; 316 }; 317 318 sdctrl@59810000 { 319 compatible = "socionext,uniphier-pro5-sdctrl", 320 "simple-mfd", "syscon"; 321 reg = <0x59810000 0x400>; 322 323 sd_clk: clock { 324 compatible = "socionext,uniphier-pro5-sd-clock"; 325 #clock-cells = <1>; 326 }; 327 328 sd_rst: reset { 329 compatible = "socionext,uniphier-pro5-sd-reset"; 330 #reset-cells = <1>; 331 }; 332 }; 333 334 perictrl@59820000 { 335 compatible = "socionext,uniphier-pro5-perictrl", 336 "simple-mfd", "syscon"; 337 reg = <0x59820000 0x200>; 338 339 peri_clk: clock { 340 compatible = "socionext,uniphier-pro5-peri-clock"; 341 #clock-cells = <1>; 342 }; 343 344 peri_rst: reset { 345 compatible = "socionext,uniphier-pro5-peri-reset"; 346 #reset-cells = <1>; 347 }; 348 }; 349 350 soc-glue@5f800000 { 351 compatible = "socionext,uniphier-pro5-soc-glue", 352 "simple-mfd", "syscon"; 353 reg = <0x5f800000 0x2000>; 354 355 pinctrl: pinctrl { 356 compatible = "socionext,uniphier-pro5-pinctrl"; 357 }; 358 }; 359 360 soc-glue@5f900000 { 361 compatible = "socionext,uniphier-pro5-soc-glue-debug", 362 "simple-mfd"; 363 #address-cells = <1>; 364 #size-cells = <1>; 365 ranges = <0 0x5f900000 0x2000>; 366 367 efuse@100 { 368 compatible = "socionext,uniphier-efuse"; 369 reg = <0x100 0x28>; 370 }; 371 372 efuse@130 { 373 compatible = "socionext,uniphier-efuse"; 374 reg = <0x130 0x8>; 375 }; 376 377 efuse@200 { 378 compatible = "socionext,uniphier-efuse"; 379 reg = <0x200 0x28>; 380 }; 381 382 efuse@300 { 383 compatible = "socionext,uniphier-efuse"; 384 reg = <0x300 0x14>; 385 }; 386 387 efuse@400 { 388 compatible = "socionext,uniphier-efuse"; 389 reg = <0x400 0x8>; 390 }; 391 }; 392 393 aidet: aidet@5fc20000 { 394 compatible = "socionext,uniphier-pro5-aidet"; 395 reg = <0x5fc20000 0x200>; 396 interrupt-controller; 397 #interrupt-cells = <2>; 398 }; 399 400 timer@60000200 { 401 compatible = "arm,cortex-a9-global-timer"; 402 reg = <0x60000200 0x20>; 403 interrupts = <1 11 0x304>; 404 clocks = <&arm_timer_clk>; 405 }; 406 407 timer@60000600 { 408 compatible = "arm,cortex-a9-twd-timer"; 409 reg = <0x60000600 0x20>; 410 interrupts = <1 13 0x304>; 411 clocks = <&arm_timer_clk>; 412 }; 413 414 intc: interrupt-controller@60001000 { 415 compatible = "arm,cortex-a9-gic"; 416 reg = <0x60001000 0x1000>, 417 <0x60000100 0x100>; 418 #interrupt-cells = <3>; 419 interrupt-controller; 420 }; 421 422 sysctrl@61840000 { 423 compatible = "socionext,uniphier-pro5-sysctrl", 424 "simple-mfd", "syscon"; 425 reg = <0x61840000 0x10000>; 426 427 sys_clk: clock { 428 compatible = "socionext,uniphier-pro5-clock"; 429 #clock-cells = <1>; 430 }; 431 432 sys_rst: reset { 433 compatible = "socionext,uniphier-pro5-reset"; 434 #reset-cells = <1>; 435 }; 436 }; 437 438 usb0: usb@65b00000 { 439 compatible = "socionext,uniphier-pro5-dwc3"; 440 status = "disabled"; 441 reg = <0x65b00000 0x1000>; 442 #address-cells = <1>; 443 #size-cells = <1>; 444 ranges; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&pinctrl_usb0>; 447 dwc3@65a00000 { 448 compatible = "snps,dwc3"; 449 reg = <0x65a00000 0x10000>; 450 interrupts = <0 134 4>; 451 dr_mode = "host"; 452 tx-fifo-resize; 453 }; 454 }; 455 456 usb1: usb@65d00000 { 457 compatible = "socionext,uniphier-pro5-dwc3"; 458 status = "disabled"; 459 reg = <0x65d00000 0x1000>; 460 #address-cells = <1>; 461 #size-cells = <1>; 462 ranges; 463 pinctrl-names = "default"; 464 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>; 465 dwc3@65c00000 { 466 compatible = "snps,dwc3"; 467 reg = <0x65c00000 0x10000>; 468 interrupts = <0 137 4>; 469 dr_mode = "host"; 470 tx-fifo-resize; 471 }; 472 }; 473 474 nand: nand@68000000 { 475 compatible = "socionext,uniphier-denali-nand-v5b"; 476 status = "disabled"; 477 reg-names = "nand_data", "denali_reg"; 478 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 479 interrupts = <0 65 4>; 480 pinctrl-names = "default"; 481 pinctrl-0 = <&pinctrl_nand2cs>; 482 clocks = <&sys_clk 2>; 483 resets = <&sys_rst 2>; 484 }; 485 486 emmc: sdhc@68400000 { 487 compatible = "socionext,uniphier-sdhc"; 488 status = "disabled"; 489 reg = <0x68400000 0x800>; 490 interrupts = <0 78 4>; 491 pinctrl-names = "default"; 492 pinctrl-0 = <&pinctrl_emmc>; 493 clocks = <&sd_clk 1>; 494 reset-names = "host"; 495 resets = <&sd_rst 1>; 496 bus-width = <8>; 497 non-removable; 498 cap-mmc-highspeed; 499 cap-mmc-hw-reset; 500 no-3-3-v; 501 }; 502 503 sd: sdhc@68800000 { 504 compatible = "socionext,uniphier-sdhc"; 505 status = "disabled"; 506 reg = <0x68800000 0x800>; 507 interrupts = <0 76 4>; 508 pinctrl-names = "default", "1.8v"; 509 pinctrl-0 = <&pinctrl_sd>; 510 pinctrl-1 = <&pinctrl_sd_1v8>; 511 clocks = <&sd_clk 0>; 512 reset-names = "host"; 513 resets = <&sd_rst 0>; 514 bus-width = <4>; 515 cap-sd-highspeed; 516 sd-uhs-sdr12; 517 sd-uhs-sdr25; 518 sd-uhs-sdr50; 519 }; 520 }; 521}; 522 523#include "uniphier-pinctrl.dtsi" 524