1/* 2 * Device Tree Source for UniPhier Pro5 SoC 3 * 4 * Copyright (C) 2015-2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ X11 8 */ 9 10/include/ "uniphier-common32.dtsi" 11 12/ { 13 compatible = "socionext,uniphier-pro5"; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu@0 { 20 device_type = "cpu"; 21 compatible = "arm,cortex-a9"; 22 reg = <0>; 23 enable-method = "psci"; 24 next-level-cache = <&l2>; 25 }; 26 27 cpu@1 { 28 device_type = "cpu"; 29 compatible = "arm,cortex-a9"; 30 reg = <1>; 31 enable-method = "psci"; 32 next-level-cache = <&l2>; 33 }; 34 }; 35 36 clocks { 37 arm_timer_clk: arm_timer_clk { 38 #clock-cells = <0>; 39 compatible = "fixed-clock"; 40 clock-frequency = <50000000>; 41 }; 42 43 i2c_clk: i2c_clk { 44 #clock-cells = <0>; 45 compatible = "fixed-clock"; 46 clock-frequency = <50000000>; 47 }; 48 }; 49}; 50 51&soc { 52 l2: l2-cache@500c0000 { 53 compatible = "socionext,uniphier-system-cache"; 54 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; 55 interrupts = <0 190 4>, <0 191 4>; 56 cache-unified; 57 cache-size = <(2 * 1024 * 1024)>; 58 cache-sets = <512>; 59 cache-line-size = <128>; 60 cache-level = <2>; 61 next-level-cache = <&l3>; 62 }; 63 64 l3: l3-cache@500c8000 { 65 compatible = "socionext,uniphier-system-cache"; 66 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; 67 interrupts = <0 174 4>, <0 175 4>; 68 cache-unified; 69 cache-size = <(2 * 1024 * 1024)>; 70 cache-sets = <512>; 71 cache-line-size = <256>; 72 cache-level = <3>; 73 }; 74 75 port0x: gpio@55000008 { 76 compatible = "socionext,uniphier-gpio"; 77 reg = <0x55000008 0x8>; 78 gpio-controller; 79 #gpio-cells = <2>; 80 }; 81 82 port1x: gpio@55000010 { 83 compatible = "socionext,uniphier-gpio"; 84 reg = <0x55000010 0x8>; 85 gpio-controller; 86 #gpio-cells = <2>; 87 }; 88 89 port2x: gpio@55000018 { 90 compatible = "socionext,uniphier-gpio"; 91 reg = <0x55000018 0x8>; 92 gpio-controller; 93 #gpio-cells = <2>; 94 }; 95 96 port3x: gpio@55000020 { 97 compatible = "socionext,uniphier-gpio"; 98 reg = <0x55000020 0x8>; 99 gpio-controller; 100 #gpio-cells = <2>; 101 }; 102 103 port4: gpio@55000028 { 104 compatible = "socionext,uniphier-gpio"; 105 reg = <0x55000028 0x8>; 106 gpio-controller; 107 #gpio-cells = <2>; 108 }; 109 110 port5x: gpio@55000030 { 111 compatible = "socionext,uniphier-gpio"; 112 reg = <0x55000030 0x8>; 113 gpio-controller; 114 #gpio-cells = <2>; 115 }; 116 117 port6x: gpio@55000038 { 118 compatible = "socionext,uniphier-gpio"; 119 reg = <0x55000038 0x8>; 120 gpio-controller; 121 #gpio-cells = <2>; 122 }; 123 124 port7x: gpio@55000040 { 125 compatible = "socionext,uniphier-gpio"; 126 reg = <0x55000040 0x8>; 127 gpio-controller; 128 #gpio-cells = <2>; 129 }; 130 131 port8x: gpio@55000048 { 132 compatible = "socionext,uniphier-gpio"; 133 reg = <0x55000048 0x8>; 134 gpio-controller; 135 #gpio-cells = <2>; 136 }; 137 138 port9x: gpio@55000050 { 139 compatible = "socionext,uniphier-gpio"; 140 reg = <0x55000050 0x8>; 141 gpio-controller; 142 #gpio-cells = <2>; 143 }; 144 145 port10x: gpio@55000058 { 146 compatible = "socionext,uniphier-gpio"; 147 reg = <0x55000058 0x8>; 148 gpio-controller; 149 #gpio-cells = <2>; 150 }; 151 152 port11x: gpio@55000060 { 153 compatible = "socionext,uniphier-gpio"; 154 reg = <0x55000060 0x8>; 155 gpio-controller; 156 #gpio-cells = <2>; 157 }; 158 159 port12x: gpio@55000068 { 160 compatible = "socionext,uniphier-gpio"; 161 reg = <0x55000068 0x8>; 162 gpio-controller; 163 #gpio-cells = <2>; 164 }; 165 166 port13x: gpio@55000070 { 167 compatible = "socionext,uniphier-gpio"; 168 reg = <0x55000070 0x8>; 169 gpio-controller; 170 #gpio-cells = <2>; 171 }; 172 173 port14x: gpio@55000078 { 174 compatible = "socionext,uniphier-gpio"; 175 reg = <0x55000078 0x8>; 176 gpio-controller; 177 #gpio-cells = <2>; 178 }; 179 180 port17x: gpio@550000a0 { 181 compatible = "socionext,uniphier-gpio"; 182 reg = <0x550000a0 0x8>; 183 gpio-controller; 184 #gpio-cells = <2>; 185 }; 186 187 port18x: gpio@550000a8 { 188 compatible = "socionext,uniphier-gpio"; 189 reg = <0x550000a8 0x8>; 190 gpio-controller; 191 #gpio-cells = <2>; 192 }; 193 194 port19x: gpio@550000b0 { 195 compatible = "socionext,uniphier-gpio"; 196 reg = <0x550000b0 0x8>; 197 gpio-controller; 198 #gpio-cells = <2>; 199 }; 200 201 port20x: gpio@550000b8 { 202 compatible = "socionext,uniphier-gpio"; 203 reg = <0x550000b8 0x8>; 204 gpio-controller; 205 #gpio-cells = <2>; 206 }; 207 208 port21x: gpio@550000c0 { 209 compatible = "socionext,uniphier-gpio"; 210 reg = <0x550000c0 0x8>; 211 gpio-controller; 212 #gpio-cells = <2>; 213 }; 214 215 port22x: gpio@550000c8 { 216 compatible = "socionext,uniphier-gpio"; 217 reg = <0x550000c8 0x8>; 218 gpio-controller; 219 #gpio-cells = <2>; 220 }; 221 222 port23x: gpio@550000d0 { 223 compatible = "socionext,uniphier-gpio"; 224 reg = <0x550000d0 0x8>; 225 gpio-controller; 226 #gpio-cells = <2>; 227 }; 228 229 port24x: gpio@550000d8 { 230 compatible = "socionext,uniphier-gpio"; 231 reg = <0x550000d8 0x8>; 232 gpio-controller; 233 #gpio-cells = <2>; 234 }; 235 236 port25x: gpio@550000e0 { 237 compatible = "socionext,uniphier-gpio"; 238 reg = <0x550000e0 0x8>; 239 gpio-controller; 240 #gpio-cells = <2>; 241 }; 242 243 port26x: gpio@550000e8 { 244 compatible = "socionext,uniphier-gpio"; 245 reg = <0x550000e8 0x8>; 246 gpio-controller; 247 #gpio-cells = <2>; 248 }; 249 250 port27x: gpio@550000f0 { 251 compatible = "socionext,uniphier-gpio"; 252 reg = <0x550000f0 0x8>; 253 gpio-controller; 254 #gpio-cells = <2>; 255 }; 256 257 port28x: gpio@550000f8 { 258 compatible = "socionext,uniphier-gpio"; 259 reg = <0x550000f8 0x8>; 260 gpio-controller; 261 #gpio-cells = <2>; 262 }; 263 264 port29x: gpio@55000100 { 265 compatible = "socionext,uniphier-gpio"; 266 reg = <0x55000100 0x8>; 267 gpio-controller; 268 #gpio-cells = <2>; 269 }; 270 271 port30x: gpio@55000108 { 272 compatible = "socionext,uniphier-gpio"; 273 reg = <0x55000108 0x8>; 274 gpio-controller; 275 #gpio-cells = <2>; 276 }; 277 278 i2c0: i2c@58780000 { 279 compatible = "socionext,uniphier-fi2c"; 280 status = "disabled"; 281 reg = <0x58780000 0x80>; 282 #address-cells = <1>; 283 #size-cells = <0>; 284 interrupts = <0 41 4>; 285 pinctrl-names = "default"; 286 pinctrl-0 = <&pinctrl_i2c0>; 287 clocks = <&i2c_clk>; 288 clock-frequency = <100000>; 289 }; 290 291 i2c1: i2c@58781000 { 292 compatible = "socionext,uniphier-fi2c"; 293 status = "disabled"; 294 reg = <0x58781000 0x80>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 interrupts = <0 42 4>; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&pinctrl_i2c1>; 300 clocks = <&i2c_clk>; 301 clock-frequency = <100000>; 302 }; 303 304 i2c2: i2c@58782000 { 305 compatible = "socionext,uniphier-fi2c"; 306 status = "disabled"; 307 reg = <0x58782000 0x80>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 interrupts = <0 43 4>; 311 pinctrl-names = "default"; 312 pinctrl-0 = <&pinctrl_i2c2>; 313 clocks = <&i2c_clk>; 314 clock-frequency = <100000>; 315 }; 316 317 i2c3: i2c@58783000 { 318 compatible = "socionext,uniphier-fi2c"; 319 status = "disabled"; 320 reg = <0x58783000 0x80>; 321 #address-cells = <1>; 322 #size-cells = <0>; 323 interrupts = <0 44 4>; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&pinctrl_i2c3>; 326 clocks = <&i2c_clk>; 327 clock-frequency = <100000>; 328 }; 329 330 /* i2c4 does not exist */ 331 332 /* chip-internal connection for DMD */ 333 i2c5: i2c@58785000 { 334 compatible = "socionext,uniphier-fi2c"; 335 reg = <0x58785000 0x80>; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 interrupts = <0 25 4>; 339 clocks = <&i2c_clk>; 340 clock-frequency = <400000>; 341 }; 342 343 /* chip-internal connection for HDMI */ 344 i2c6: i2c@58786000 { 345 compatible = "socionext,uniphier-fi2c"; 346 reg = <0x58786000 0x80>; 347 #address-cells = <1>; 348 #size-cells = <0>; 349 interrupts = <0 26 4>; 350 clocks = <&i2c_clk>; 351 clock-frequency = <400000>; 352 }; 353 354 aidet@5fc20000 { 355 compatible = "simple-mfd", "syscon"; 356 reg = <0x5fc20000 0x200>; 357 }; 358 359 emmc: sdhc@68400000 { 360 compatible = "socionext,uniphier-sdhc"; 361 status = "disabled"; 362 reg = <0x68400000 0x800>; 363 interrupts = <0 78 4>; 364 pinctrl-names = "default"; 365 pinctrl-0 = <&pinctrl_emmc>; 366 clocks = <&mio_clk 1>; 367 reset-names = "host", "hw-reset"; 368 resets = <&mio_rst 1>, <&mio_rst 6>; 369 bus-width = <8>; 370 non-removable; 371 }; 372 373 sd: sdhc@68800000 { 374 compatible = "socionext,uniphier-sdhc"; 375 status = "disabled"; 376 reg = <0x68800000 0x800>; 377 interrupts = <0 76 4>; 378 pinctrl-names = "default", "1.8v"; 379 pinctrl-0 = <&pinctrl_sd>; 380 pinctrl-1 = <&pinctrl_sd_1v8>; 381 clocks = <&mio_clk 0>; 382 reset-names = "host"; 383 resets = <&mio_rst 0>; 384 bus-width = <4>; 385 }; 386 387 usb0: usb@65a00000 { 388 compatible = "socionext,uniphier-xhci", "generic-xhci"; 389 status = "disabled"; 390 reg = <0x65a00000 0x100>; 391 interrupts = <0 134 4>; 392 pinctrl-names = "default"; 393 pinctrl-0 = <&pinctrl_usb0>; 394 }; 395 396 usb1: usb@65c00000 { 397 compatible = "socionext,uniphier-xhci", "generic-xhci"; 398 status = "disabled"; 399 reg = <0x65c00000 0x100>; 400 interrupts = <0 137 4>; 401 pinctrl-names = "default"; 402 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>; 403 }; 404}; 405 406&refclk { 407 clock-frequency = <20000000>; 408}; 409 410&serial0 { 411 clock-frequency = <73728000>; 412}; 413 414&serial1 { 415 clock-frequency = <73728000>; 416}; 417 418&serial2 { 419 clock-frequency = <73728000>; 420}; 421 422&serial3 { 423 clock-frequency = <73728000>; 424}; 425 426&mio_clk { 427 compatible = "socionext,uniphier-pro5-mio-clock"; 428}; 429 430&mio_rst { 431 compatible = "socionext,uniphier-pro5-mio-reset"; 432}; 433 434&peri_clk { 435 compatible = "socionext,uniphier-pro5-peri-clock"; 436}; 437 438&peri_rst { 439 compatible = "socionext,uniphier-pro5-peri-reset"; 440}; 441 442&pinctrl { 443 compatible = "socionext,uniphier-pro5-pinctrl"; 444}; 445 446&sys_clk { 447 compatible = "socionext,uniphier-pro5-clock"; 448}; 449 450&sys_rst { 451 compatible = "socionext,uniphier-pro5-reset"; 452}; 453