1/* 2 * Device Tree Source for UniPhier Pro5 SoC 3 * 4 * Copyright (C) 2015-2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 */ 9 10/ { 11 compatible = "socionext,uniphier-pro5"; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu@0 { 20 device_type = "cpu"; 21 compatible = "arm,cortex-a9"; 22 reg = <0>; 23 clocks = <&sys_clk 32>; 24 enable-method = "psci"; 25 next-level-cache = <&l2>; 26 operating-points-v2 = <&cpu_opp>; 27 }; 28 29 cpu@1 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a9"; 32 reg = <1>; 33 clocks = <&sys_clk 32>; 34 enable-method = "psci"; 35 next-level-cache = <&l2>; 36 operating-points-v2 = <&cpu_opp>; 37 }; 38 }; 39 40 cpu_opp: opp-table { 41 compatible = "operating-points-v2"; 42 opp-shared; 43 44 opp-100000000 { 45 opp-hz = /bits/ 64 <100000000>; 46 clock-latency-ns = <300>; 47 }; 48 opp-116667000 { 49 opp-hz = /bits/ 64 <116667000>; 50 clock-latency-ns = <300>; 51 }; 52 opp-150000000 { 53 opp-hz = /bits/ 64 <150000000>; 54 clock-latency-ns = <300>; 55 }; 56 opp-175000000 { 57 opp-hz = /bits/ 64 <175000000>; 58 clock-latency-ns = <300>; 59 }; 60 opp-200000000 { 61 opp-hz = /bits/ 64 <200000000>; 62 clock-latency-ns = <300>; 63 }; 64 opp-233334000 { 65 opp-hz = /bits/ 64 <233334000>; 66 clock-latency-ns = <300>; 67 }; 68 opp-300000000 { 69 opp-hz = /bits/ 64 <300000000>; 70 clock-latency-ns = <300>; 71 }; 72 opp-350000000 { 73 opp-hz = /bits/ 64 <350000000>; 74 clock-latency-ns = <300>; 75 }; 76 opp-400000000 { 77 opp-hz = /bits/ 64 <400000000>; 78 clock-latency-ns = <300>; 79 }; 80 opp-466667000 { 81 opp-hz = /bits/ 64 <466667000>; 82 clock-latency-ns = <300>; 83 }; 84 opp-600000000 { 85 opp-hz = /bits/ 64 <600000000>; 86 clock-latency-ns = <300>; 87 }; 88 opp-700000000 { 89 opp-hz = /bits/ 64 <700000000>; 90 clock-latency-ns = <300>; 91 }; 92 opp-800000000 { 93 opp-hz = /bits/ 64 <800000000>; 94 clock-latency-ns = <300>; 95 }; 96 opp-933334000 { 97 opp-hz = /bits/ 64 <933334000>; 98 clock-latency-ns = <300>; 99 }; 100 opp-1200000000 { 101 opp-hz = /bits/ 64 <1200000000>; 102 clock-latency-ns = <300>; 103 }; 104 opp-1400000000 { 105 opp-hz = /bits/ 64 <1400000000>; 106 clock-latency-ns = <300>; 107 }; 108 }; 109 110 psci { 111 compatible = "arm,psci-0.2"; 112 method = "smc"; 113 }; 114 115 clocks { 116 refclk: ref { 117 compatible = "fixed-clock"; 118 #clock-cells = <0>; 119 clock-frequency = <20000000>; 120 }; 121 122 arm_timer_clk: arm-timer { 123 #clock-cells = <0>; 124 compatible = "fixed-clock"; 125 clock-frequency = <50000000>; 126 }; 127 }; 128 129 soc { 130 compatible = "simple-bus"; 131 #address-cells = <1>; 132 #size-cells = <1>; 133 ranges; 134 interrupt-parent = <&intc>; 135 136 l2: l2-cache@500c0000 { 137 compatible = "socionext,uniphier-system-cache"; 138 reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, 139 <0x506c0000 0x400>; 140 interrupts = <0 190 4>, <0 191 4>; 141 cache-unified; 142 cache-size = <(2 * 1024 * 1024)>; 143 cache-sets = <512>; 144 cache-line-size = <128>; 145 cache-level = <2>; 146 next-level-cache = <&l3>; 147 }; 148 149 l3: l3-cache@500c8000 { 150 compatible = "socionext,uniphier-system-cache"; 151 reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, 152 <0x506c8000 0x400>; 153 interrupts = <0 174 4>, <0 175 4>; 154 cache-unified; 155 cache-size = <(2 * 1024 * 1024)>; 156 cache-sets = <512>; 157 cache-line-size = <256>; 158 cache-level = <3>; 159 }; 160 161 serial0: serial@54006800 { 162 compatible = "socionext,uniphier-uart"; 163 status = "disabled"; 164 reg = <0x54006800 0x40>; 165 interrupts = <0 33 4>; 166 pinctrl-names = "default"; 167 pinctrl-0 = <&pinctrl_uart0>; 168 clocks = <&peri_clk 0>; 169 clock-frequency = <73728000>; 170 resets = <&peri_rst 0>; 171 }; 172 173 serial1: serial@54006900 { 174 compatible = "socionext,uniphier-uart"; 175 status = "disabled"; 176 reg = <0x54006900 0x40>; 177 interrupts = <0 35 4>; 178 pinctrl-names = "default"; 179 pinctrl-0 = <&pinctrl_uart1>; 180 clocks = <&peri_clk 1>; 181 clock-frequency = <73728000>; 182 resets = <&peri_rst 1>; 183 }; 184 185 serial2: serial@54006a00 { 186 compatible = "socionext,uniphier-uart"; 187 status = "disabled"; 188 reg = <0x54006a00 0x40>; 189 interrupts = <0 37 4>; 190 pinctrl-names = "default"; 191 pinctrl-0 = <&pinctrl_uart2>; 192 clocks = <&peri_clk 2>; 193 clock-frequency = <73728000>; 194 resets = <&peri_rst 2>; 195 }; 196 197 serial3: serial@54006b00 { 198 compatible = "socionext,uniphier-uart"; 199 status = "disabled"; 200 reg = <0x54006b00 0x40>; 201 interrupts = <0 177 4>; 202 pinctrl-names = "default"; 203 pinctrl-0 = <&pinctrl_uart3>; 204 clocks = <&peri_clk 3>; 205 clock-frequency = <73728000>; 206 resets = <&peri_rst 3>; 207 }; 208 209 gpio: gpio@55000000 { 210 compatible = "socionext,uniphier-gpio"; 211 reg = <0x55000000 0x200>; 212 interrupt-parent = <&aidet>; 213 interrupt-controller; 214 #interrupt-cells = <2>; 215 gpio-controller; 216 #gpio-cells = <2>; 217 gpio-ranges = <&pinctrl 0 0 0>; 218 gpio-ranges-group-names = "gpio_range"; 219 ngpios = <248>; 220 socionext,interrupt-ranges = <0 48 16>, <16 154 5>; 221 }; 222 223 i2c0: i2c@58780000 { 224 compatible = "socionext,uniphier-fi2c"; 225 status = "disabled"; 226 reg = <0x58780000 0x80>; 227 #address-cells = <1>; 228 #size-cells = <0>; 229 interrupts = <0 41 4>; 230 pinctrl-names = "default"; 231 pinctrl-0 = <&pinctrl_i2c0>; 232 clocks = <&peri_clk 4>; 233 resets = <&peri_rst 4>; 234 clock-frequency = <100000>; 235 }; 236 237 i2c1: i2c@58781000 { 238 compatible = "socionext,uniphier-fi2c"; 239 status = "disabled"; 240 reg = <0x58781000 0x80>; 241 #address-cells = <1>; 242 #size-cells = <0>; 243 interrupts = <0 42 4>; 244 pinctrl-names = "default"; 245 pinctrl-0 = <&pinctrl_i2c1>; 246 clocks = <&peri_clk 5>; 247 resets = <&peri_rst 5>; 248 clock-frequency = <100000>; 249 }; 250 251 i2c2: i2c@58782000 { 252 compatible = "socionext,uniphier-fi2c"; 253 status = "disabled"; 254 reg = <0x58782000 0x80>; 255 #address-cells = <1>; 256 #size-cells = <0>; 257 interrupts = <0 43 4>; 258 pinctrl-names = "default"; 259 pinctrl-0 = <&pinctrl_i2c2>; 260 clocks = <&peri_clk 6>; 261 resets = <&peri_rst 6>; 262 clock-frequency = <100000>; 263 }; 264 265 i2c3: i2c@58783000 { 266 compatible = "socionext,uniphier-fi2c"; 267 status = "disabled"; 268 reg = <0x58783000 0x80>; 269 #address-cells = <1>; 270 #size-cells = <0>; 271 interrupts = <0 44 4>; 272 pinctrl-names = "default"; 273 pinctrl-0 = <&pinctrl_i2c3>; 274 clocks = <&peri_clk 7>; 275 resets = <&peri_rst 7>; 276 clock-frequency = <100000>; 277 }; 278 279 /* i2c4 does not exist */ 280 281 /* chip-internal connection for DMD */ 282 i2c5: i2c@58785000 { 283 compatible = "socionext,uniphier-fi2c"; 284 reg = <0x58785000 0x80>; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 interrupts = <0 25 4>; 288 clocks = <&peri_clk 9>; 289 resets = <&peri_rst 9>; 290 clock-frequency = <400000>; 291 }; 292 293 /* chip-internal connection for HDMI */ 294 i2c6: i2c@58786000 { 295 compatible = "socionext,uniphier-fi2c"; 296 reg = <0x58786000 0x80>; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 interrupts = <0 26 4>; 300 clocks = <&peri_clk 10>; 301 resets = <&peri_rst 10>; 302 clock-frequency = <400000>; 303 }; 304 305 system_bus: system-bus@58c00000 { 306 compatible = "socionext,uniphier-system-bus"; 307 status = "disabled"; 308 reg = <0x58c00000 0x400>; 309 #address-cells = <2>; 310 #size-cells = <1>; 311 pinctrl-names = "default"; 312 pinctrl-0 = <&pinctrl_system_bus>; 313 }; 314 315 smpctrl@59801000 { 316 compatible = "socionext,uniphier-smpctrl"; 317 reg = <0x59801000 0x400>; 318 }; 319 320 sdctrl@59810000 { 321 compatible = "socionext,uniphier-pro5-sdctrl", 322 "simple-mfd", "syscon"; 323 reg = <0x59810000 0x400>; 324 325 sd_clk: clock { 326 compatible = "socionext,uniphier-pro5-sd-clock"; 327 #clock-cells = <1>; 328 }; 329 330 sd_rst: reset { 331 compatible = "socionext,uniphier-pro5-sd-reset"; 332 #reset-cells = <1>; 333 }; 334 }; 335 336 perictrl@59820000 { 337 compatible = "socionext,uniphier-pro5-perictrl", 338 "simple-mfd", "syscon"; 339 reg = <0x59820000 0x200>; 340 341 peri_clk: clock { 342 compatible = "socionext,uniphier-pro5-peri-clock"; 343 #clock-cells = <1>; 344 }; 345 346 peri_rst: reset { 347 compatible = "socionext,uniphier-pro5-peri-reset"; 348 #reset-cells = <1>; 349 }; 350 }; 351 352 soc-glue@5f800000 { 353 compatible = "socionext,uniphier-pro5-soc-glue", 354 "simple-mfd", "syscon"; 355 reg = <0x5f800000 0x2000>; 356 357 pinctrl: pinctrl { 358 compatible = "socionext,uniphier-pro5-pinctrl"; 359 }; 360 }; 361 362 aidet: aidet@5fc20000 { 363 compatible = "socionext,uniphier-pro5-aidet"; 364 reg = <0x5fc20000 0x200>; 365 interrupt-controller; 366 #interrupt-cells = <2>; 367 }; 368 369 timer@60000200 { 370 compatible = "arm,cortex-a9-global-timer"; 371 reg = <0x60000200 0x20>; 372 interrupts = <1 11 0x304>; 373 clocks = <&arm_timer_clk>; 374 }; 375 376 timer@60000600 { 377 compatible = "arm,cortex-a9-twd-timer"; 378 reg = <0x60000600 0x20>; 379 interrupts = <1 13 0x304>; 380 clocks = <&arm_timer_clk>; 381 }; 382 383 intc: interrupt-controller@60001000 { 384 compatible = "arm,cortex-a9-gic"; 385 reg = <0x60001000 0x1000>, 386 <0x60000100 0x100>; 387 #interrupt-cells = <3>; 388 interrupt-controller; 389 }; 390 391 sysctrl@61840000 { 392 compatible = "socionext,uniphier-pro5-sysctrl", 393 "simple-mfd", "syscon"; 394 reg = <0x61840000 0x10000>; 395 396 sys_clk: clock { 397 compatible = "socionext,uniphier-pro5-clock"; 398 #clock-cells = <1>; 399 }; 400 401 sys_rst: reset { 402 compatible = "socionext,uniphier-pro5-reset"; 403 #reset-cells = <1>; 404 }; 405 }; 406 407 usb0: usb@65b00000 { 408 compatible = "socionext,uniphier-pro5-dwc3"; 409 status = "disabled"; 410 reg = <0x65b00000 0x1000>; 411 #address-cells = <1>; 412 #size-cells = <1>; 413 ranges; 414 pinctrl-names = "default"; 415 pinctrl-0 = <&pinctrl_usb0>; 416 dwc3@65a00000 { 417 compatible = "snps,dwc3"; 418 reg = <0x65a00000 0x10000>; 419 interrupts = <0 134 4>; 420 dr_mode = "host"; 421 tx-fifo-resize; 422 }; 423 }; 424 425 usb1: usb@65d00000 { 426 compatible = "socionext,uniphier-pro5-dwc3"; 427 status = "disabled"; 428 reg = <0x65d00000 0x1000>; 429 #address-cells = <1>; 430 #size-cells = <1>; 431 ranges; 432 pinctrl-names = "default"; 433 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb2>; 434 dwc3@65c00000 { 435 compatible = "snps,dwc3"; 436 reg = <0x65c00000 0x10000>; 437 interrupts = <0 137 4>; 438 dr_mode = "host"; 439 tx-fifo-resize; 440 }; 441 }; 442 443 nand: nand@68000000 { 444 compatible = "socionext,uniphier-denali-nand-v5b"; 445 status = "disabled"; 446 reg-names = "nand_data", "denali_reg"; 447 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 448 interrupts = <0 65 4>; 449 pinctrl-names = "default"; 450 pinctrl-0 = <&pinctrl_nand2cs>; 451 clocks = <&sys_clk 2>; 452 resets = <&sys_rst 2>; 453 }; 454 455 emmc: sdhc@68400000 { 456 compatible = "socionext,uniphier-sdhc"; 457 status = "disabled"; 458 reg = <0x68400000 0x800>; 459 interrupts = <0 78 4>; 460 pinctrl-names = "default"; 461 pinctrl-0 = <&pinctrl_emmc>; 462 clocks = <&sd_clk 1>; 463 reset-names = "host"; 464 resets = <&sd_rst 1>; 465 bus-width = <8>; 466 non-removable; 467 cap-mmc-highspeed; 468 cap-mmc-hw-reset; 469 no-3-3-v; 470 }; 471 472 sd: sdhc@68800000 { 473 compatible = "socionext,uniphier-sdhc"; 474 status = "disabled"; 475 reg = <0x68800000 0x800>; 476 interrupts = <0 76 4>; 477 pinctrl-names = "default", "1.8v"; 478 pinctrl-0 = <&pinctrl_sd>; 479 pinctrl-1 = <&pinctrl_sd_1v8>; 480 clocks = <&sd_clk 0>; 481 reset-names = "host"; 482 resets = <&sd_rst 0>; 483 bus-width = <4>; 484 cap-sd-highspeed; 485 sd-uhs-sdr12; 486 sd-uhs-sdr25; 487 sd-uhs-sdr50; 488 }; 489 }; 490}; 491 492#include "uniphier-pinctrl.dtsi" 493