1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Device Tree Source for UniPhier Pro4 SoC 4// 5// Copyright (C) 2015-2016 Socionext Inc. 6// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 8#include <dt-bindings/gpio/uniphier-gpio.h> 9 10/ { 11 compatible = "socionext,uniphier-pro4"; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu@0 { 20 device_type = "cpu"; 21 compatible = "arm,cortex-a9"; 22 reg = <0>; 23 enable-method = "psci"; 24 next-level-cache = <&l2>; 25 }; 26 27 cpu@1 { 28 device_type = "cpu"; 29 compatible = "arm,cortex-a9"; 30 reg = <1>; 31 enable-method = "psci"; 32 next-level-cache = <&l2>; 33 }; 34 }; 35 36 psci { 37 compatible = "arm,psci-0.2"; 38 method = "smc"; 39 }; 40 41 clocks { 42 refclk: ref { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <25000000>; 46 }; 47 48 arm_timer_clk: arm-timer { 49 #clock-cells = <0>; 50 compatible = "fixed-clock"; 51 clock-frequency = <50000000>; 52 }; 53 }; 54 55 soc { 56 compatible = "simple-bus"; 57 #address-cells = <1>; 58 #size-cells = <1>; 59 ranges; 60 interrupt-parent = <&intc>; 61 62 l2: l2-cache@500c0000 { 63 compatible = "socionext,uniphier-system-cache"; 64 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, 65 <0x506c0000 0x400>; 66 interrupts = <0 174 4>, <0 175 4>; 67 cache-unified; 68 cache-size = <(768 * 1024)>; 69 cache-sets = <256>; 70 cache-line-size = <128>; 71 cache-level = <2>; 72 }; 73 74 serial0: serial@54006800 { 75 compatible = "socionext,uniphier-uart"; 76 status = "disabled"; 77 reg = <0x54006800 0x40>; 78 interrupts = <0 33 4>; 79 pinctrl-names = "default"; 80 pinctrl-0 = <&pinctrl_uart0>; 81 clocks = <&peri_clk 0>; 82 resets = <&peri_rst 0>; 83 }; 84 85 serial1: serial@54006900 { 86 compatible = "socionext,uniphier-uart"; 87 status = "disabled"; 88 reg = <0x54006900 0x40>; 89 interrupts = <0 35 4>; 90 pinctrl-names = "default"; 91 pinctrl-0 = <&pinctrl_uart1>; 92 clocks = <&peri_clk 1>; 93 resets = <&peri_rst 1>; 94 }; 95 96 serial2: serial@54006a00 { 97 compatible = "socionext,uniphier-uart"; 98 status = "disabled"; 99 reg = <0x54006a00 0x40>; 100 interrupts = <0 37 4>; 101 pinctrl-names = "default"; 102 pinctrl-0 = <&pinctrl_uart2>; 103 clocks = <&peri_clk 2>; 104 resets = <&peri_rst 2>; 105 }; 106 107 serial3: serial@54006b00 { 108 compatible = "socionext,uniphier-uart"; 109 status = "disabled"; 110 reg = <0x54006b00 0x40>; 111 interrupts = <0 177 4>; 112 pinctrl-names = "default"; 113 pinctrl-0 = <&pinctrl_uart3>; 114 clocks = <&peri_clk 3>; 115 resets = <&peri_rst 3>; 116 }; 117 118 gpio: gpio@55000000 { 119 compatible = "socionext,uniphier-gpio"; 120 reg = <0x55000000 0x200>; 121 interrupt-parent = <&aidet>; 122 interrupt-controller; 123 #interrupt-cells = <2>; 124 gpio-controller; 125 #gpio-cells = <2>; 126 gpio-ranges = <&pinctrl 0 0 0>; 127 gpio-ranges-group-names = "gpio_range"; 128 ngpios = <248>; 129 socionext,interrupt-ranges = <0 48 16>, <16 154 5>; 130 }; 131 132 i2c0: i2c@58780000 { 133 compatible = "socionext,uniphier-fi2c"; 134 status = "disabled"; 135 reg = <0x58780000 0x80>; 136 #address-cells = <1>; 137 #size-cells = <0>; 138 interrupts = <0 41 4>; 139 pinctrl-names = "default"; 140 pinctrl-0 = <&pinctrl_i2c0>; 141 clocks = <&peri_clk 4>; 142 resets = <&peri_rst 4>; 143 clock-frequency = <100000>; 144 }; 145 146 i2c1: i2c@58781000 { 147 compatible = "socionext,uniphier-fi2c"; 148 status = "disabled"; 149 reg = <0x58781000 0x80>; 150 #address-cells = <1>; 151 #size-cells = <0>; 152 interrupts = <0 42 4>; 153 pinctrl-names = "default"; 154 pinctrl-0 = <&pinctrl_i2c1>; 155 clocks = <&peri_clk 5>; 156 resets = <&peri_rst 5>; 157 clock-frequency = <100000>; 158 }; 159 160 i2c2: i2c@58782000 { 161 compatible = "socionext,uniphier-fi2c"; 162 status = "disabled"; 163 reg = <0x58782000 0x80>; 164 #address-cells = <1>; 165 #size-cells = <0>; 166 interrupts = <0 43 4>; 167 pinctrl-names = "default"; 168 pinctrl-0 = <&pinctrl_i2c2>; 169 clocks = <&peri_clk 6>; 170 resets = <&peri_rst 6>; 171 clock-frequency = <100000>; 172 }; 173 174 i2c3: i2c@58783000 { 175 compatible = "socionext,uniphier-fi2c"; 176 status = "disabled"; 177 reg = <0x58783000 0x80>; 178 #address-cells = <1>; 179 #size-cells = <0>; 180 interrupts = <0 44 4>; 181 pinctrl-names = "default"; 182 pinctrl-0 = <&pinctrl_i2c3>; 183 clocks = <&peri_clk 7>; 184 resets = <&peri_rst 7>; 185 clock-frequency = <100000>; 186 }; 187 188 /* i2c4 does not exist */ 189 190 /* chip-internal connection for DMD */ 191 i2c5: i2c@58785000 { 192 compatible = "socionext,uniphier-fi2c"; 193 reg = <0x58785000 0x80>; 194 #address-cells = <1>; 195 #size-cells = <0>; 196 interrupts = <0 25 4>; 197 clocks = <&peri_clk 9>; 198 resets = <&peri_rst 9>; 199 clock-frequency = <400000>; 200 }; 201 202 /* chip-internal connection for HDMI */ 203 i2c6: i2c@58786000 { 204 compatible = "socionext,uniphier-fi2c"; 205 reg = <0x58786000 0x80>; 206 #address-cells = <1>; 207 #size-cells = <0>; 208 interrupts = <0 26 4>; 209 clocks = <&peri_clk 10>; 210 resets = <&peri_rst 10>; 211 clock-frequency = <400000>; 212 }; 213 214 system_bus: system-bus@58c00000 { 215 compatible = "socionext,uniphier-system-bus"; 216 status = "disabled"; 217 reg = <0x58c00000 0x400>; 218 #address-cells = <2>; 219 #size-cells = <1>; 220 pinctrl-names = "default"; 221 pinctrl-0 = <&pinctrl_system_bus>; 222 }; 223 224 smpctrl@59801000 { 225 compatible = "socionext,uniphier-smpctrl"; 226 reg = <0x59801000 0x400>; 227 }; 228 229 mioctrl@59810000 { 230 compatible = "socionext,uniphier-pro4-mioctrl", 231 "simple-mfd", "syscon"; 232 reg = <0x59810000 0x800>; 233 234 mio_clk: clock { 235 compatible = "socionext,uniphier-pro4-mio-clock"; 236 #clock-cells = <1>; 237 }; 238 239 mio_rst: reset { 240 compatible = "socionext,uniphier-pro4-mio-reset"; 241 #reset-cells = <1>; 242 }; 243 }; 244 245 perictrl@59820000 { 246 compatible = "socionext,uniphier-pro4-perictrl", 247 "simple-mfd", "syscon"; 248 reg = <0x59820000 0x200>; 249 250 peri_clk: clock { 251 compatible = "socionext,uniphier-pro4-peri-clock"; 252 #clock-cells = <1>; 253 }; 254 255 peri_rst: reset { 256 compatible = "socionext,uniphier-pro4-peri-reset"; 257 #reset-cells = <1>; 258 }; 259 }; 260 261 sd: sdhc@5a400000 { 262 compatible = "socionext,uniphier-sd-v2.91"; 263 status = "disabled"; 264 reg = <0x5a400000 0x200>; 265 interrupts = <0 76 4>; 266 pinctrl-names = "default", "uhs"; 267 pinctrl-0 = <&pinctrl_sd>; 268 pinctrl-1 = <&pinctrl_sd_uhs>; 269 clocks = <&mio_clk 0>; 270 reset-names = "host", "bridge"; 271 resets = <&mio_rst 0>, <&mio_rst 3>; 272 bus-width = <4>; 273 cap-sd-highspeed; 274 sd-uhs-sdr12; 275 sd-uhs-sdr25; 276 sd-uhs-sdr50; 277 }; 278 279 emmc: sdhc@5a500000 { 280 compatible = "socionext,uniphier-sd-v2.91"; 281 status = "disabled"; 282 reg = <0x5a500000 0x200>; 283 interrupts = <0 78 4>; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&pinctrl_emmc>; 286 clocks = <&mio_clk 1>; 287 reset-names = "host", "bridge", "hw"; 288 resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>; 289 bus-width = <8>; 290 cap-mmc-highspeed; 291 cap-mmc-hw-reset; 292 non-removable; 293 }; 294 295 sd1: sdhc@5a600000 { 296 compatible = "socionext,uniphier-sd-v2.91"; 297 status = "disabled"; 298 reg = <0x5a600000 0x200>; 299 interrupts = <0 85 4>; 300 pinctrl-names = "default"; 301 pinctrl-0 = <&pinctrl_sd1>; 302 clocks = <&mio_clk 2>; 303 reset-names = "host", "bridge"; 304 resets = <&mio_rst 2>, <&mio_rst 5>; 305 bus-width = <4>; 306 cap-sd-highspeed; 307 }; 308 309 usb2: usb@5a800100 { 310 compatible = "socionext,uniphier-ehci", "generic-ehci"; 311 status = "disabled"; 312 reg = <0x5a800100 0x100>; 313 interrupts = <0 80 4>; 314 pinctrl-names = "default"; 315 pinctrl-0 = <&pinctrl_usb2>; 316 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, 317 <&mio_clk 12>; 318 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 319 <&mio_rst 12>; 320 has-transaction-translator; 321 }; 322 323 usb3: usb@5a810100 { 324 compatible = "socionext,uniphier-ehci", "generic-ehci"; 325 status = "disabled"; 326 reg = <0x5a810100 0x100>; 327 interrupts = <0 81 4>; 328 pinctrl-names = "default"; 329 pinctrl-0 = <&pinctrl_usb3>; 330 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, 331 <&mio_clk 13>; 332 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 333 <&mio_rst 13>; 334 has-transaction-translator; 335 }; 336 337 soc_glue: soc-glue@5f800000 { 338 compatible = "socionext,uniphier-pro4-soc-glue", 339 "simple-mfd", "syscon"; 340 reg = <0x5f800000 0x2000>; 341 342 pinctrl: pinctrl { 343 compatible = "socionext,uniphier-pro4-pinctrl"; 344 }; 345 }; 346 347 soc-glue@5f900000 { 348 compatible = "socionext,uniphier-pro4-soc-glue-debug", 349 "simple-mfd"; 350 #address-cells = <1>; 351 #size-cells = <1>; 352 ranges = <0 0x5f900000 0x2000>; 353 354 efuse@100 { 355 compatible = "socionext,uniphier-efuse"; 356 reg = <0x100 0x28>; 357 }; 358 359 efuse@130 { 360 compatible = "socionext,uniphier-efuse"; 361 reg = <0x130 0x8>; 362 }; 363 364 efuse@200 { 365 compatible = "socionext,uniphier-efuse"; 366 reg = <0x200 0x14>; 367 }; 368 }; 369 370 aidet: aidet@5fc20000 { 371 compatible = "socionext,uniphier-pro4-aidet"; 372 reg = <0x5fc20000 0x200>; 373 interrupt-controller; 374 #interrupt-cells = <2>; 375 }; 376 377 timer@60000200 { 378 compatible = "arm,cortex-a9-global-timer"; 379 reg = <0x60000200 0x20>; 380 interrupts = <1 11 0x304>; 381 clocks = <&arm_timer_clk>; 382 }; 383 384 timer@60000600 { 385 compatible = "arm,cortex-a9-twd-timer"; 386 reg = <0x60000600 0x20>; 387 interrupts = <1 13 0x304>; 388 clocks = <&arm_timer_clk>; 389 }; 390 391 intc: interrupt-controller@60001000 { 392 compatible = "arm,cortex-a9-gic"; 393 reg = <0x60001000 0x1000>, 394 <0x60000100 0x100>; 395 #interrupt-cells = <3>; 396 interrupt-controller; 397 }; 398 399 sysctrl@61840000 { 400 compatible = "socionext,uniphier-pro4-sysctrl", 401 "simple-mfd", "syscon"; 402 reg = <0x61840000 0x10000>; 403 404 sys_clk: clock { 405 compatible = "socionext,uniphier-pro4-clock"; 406 #clock-cells = <1>; 407 }; 408 409 sys_rst: reset { 410 compatible = "socionext,uniphier-pro4-reset"; 411 #reset-cells = <1>; 412 }; 413 }; 414 415 eth: ethernet@65000000 { 416 compatible = "socionext,uniphier-pro4-ave4"; 417 status = "disabled"; 418 reg = <0x65000000 0x8500>; 419 interrupts = <0 66 4>; 420 pinctrl-names = "default"; 421 pinctrl-0 = <&pinctrl_ether_rgmii>; 422 clock-names = "gio", "ether", "ether-gb", "ether-phy"; 423 clocks = <&sys_clk 12>, <&sys_clk 6>, <&sys_clk 7>, 424 <&sys_clk 10>; 425 reset-names = "gio", "ether"; 426 resets = <&sys_rst 12>, <&sys_rst 6>; 427 phy-mode = "rgmii"; 428 local-mac-address = [00 00 00 00 00 00]; 429 socionext,syscon-phy-mode = <&soc_glue 0>; 430 431 mdio: mdio { 432 #address-cells = <1>; 433 #size-cells = <0>; 434 }; 435 }; 436 437 usb0: usb@65b00000 { 438 compatible = "socionext,uniphier-pro4-dwc3"; 439 status = "disabled"; 440 reg = <0x65b00000 0x1000>; 441 #address-cells = <1>; 442 #size-cells = <1>; 443 ranges; 444 pinctrl-names = "default"; 445 pinctrl-0 = <&pinctrl_usb0>; 446 dwc3@65a00000 { 447 compatible = "snps,dwc3"; 448 reg = <0x65a00000 0x10000>; 449 interrupts = <0 134 4>; 450 dr_mode = "host"; 451 tx-fifo-resize; 452 }; 453 }; 454 455 usb1: usb@65d00000 { 456 compatible = "socionext,uniphier-pro4-dwc3"; 457 status = "disabled"; 458 reg = <0x65d00000 0x1000>; 459 #address-cells = <1>; 460 #size-cells = <1>; 461 ranges; 462 pinctrl-names = "default"; 463 pinctrl-0 = <&pinctrl_usb1>; 464 dwc3@65c00000 { 465 compatible = "snps,dwc3"; 466 reg = <0x65c00000 0x10000>; 467 interrupts = <0 137 4>; 468 dr_mode = "host"; 469 tx-fifo-resize; 470 }; 471 }; 472 473 nand: nand@68000000 { 474 compatible = "socionext,uniphier-denali-nand-v5a"; 475 status = "disabled"; 476 reg-names = "nand_data", "denali_reg"; 477 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 478 interrupts = <0 65 4>; 479 pinctrl-names = "default"; 480 pinctrl-0 = <&pinctrl_nand>; 481 clocks = <&sys_clk 2>; 482 resets = <&sys_rst 2>; 483 }; 484 }; 485}; 486 487#include "uniphier-pinctrl.dtsi" 488