1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Device Tree Source for UniPhier Pro4 SoC 4// 5// Copyright (C) 2015-2016 Socionext Inc. 6// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 8#include <dt-bindings/gpio/uniphier-gpio.h> 9 10/ { 11 compatible = "socionext,uniphier-pro4"; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu@0 { 20 device_type = "cpu"; 21 compatible = "arm,cortex-a9"; 22 reg = <0>; 23 enable-method = "psci"; 24 next-level-cache = <&l2>; 25 }; 26 27 cpu@1 { 28 device_type = "cpu"; 29 compatible = "arm,cortex-a9"; 30 reg = <1>; 31 enable-method = "psci"; 32 next-level-cache = <&l2>; 33 }; 34 }; 35 36 psci { 37 compatible = "arm,psci-0.2"; 38 method = "smc"; 39 }; 40 41 clocks { 42 refclk: ref { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <25000000>; 46 }; 47 48 arm_timer_clk: arm-timer { 49 #clock-cells = <0>; 50 compatible = "fixed-clock"; 51 clock-frequency = <50000000>; 52 }; 53 }; 54 55 soc { 56 compatible = "simple-bus"; 57 #address-cells = <1>; 58 #size-cells = <1>; 59 ranges; 60 interrupt-parent = <&intc>; 61 62 l2: l2-cache@500c0000 { 63 compatible = "socionext,uniphier-system-cache"; 64 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, 65 <0x506c0000 0x400>; 66 interrupts = <0 174 4>, <0 175 4>; 67 cache-unified; 68 cache-size = <(768 * 1024)>; 69 cache-sets = <256>; 70 cache-line-size = <128>; 71 cache-level = <2>; 72 }; 73 74 serial0: serial@54006800 { 75 compatible = "socionext,uniphier-uart"; 76 status = "disabled"; 77 reg = <0x54006800 0x40>; 78 interrupts = <0 33 4>; 79 pinctrl-names = "default"; 80 pinctrl-0 = <&pinctrl_uart0>; 81 clocks = <&peri_clk 0>; 82 resets = <&peri_rst 0>; 83 }; 84 85 serial1: serial@54006900 { 86 compatible = "socionext,uniphier-uart"; 87 status = "disabled"; 88 reg = <0x54006900 0x40>; 89 interrupts = <0 35 4>; 90 pinctrl-names = "default"; 91 pinctrl-0 = <&pinctrl_uart1>; 92 clocks = <&peri_clk 1>; 93 resets = <&peri_rst 1>; 94 }; 95 96 serial2: serial@54006a00 { 97 compatible = "socionext,uniphier-uart"; 98 status = "disabled"; 99 reg = <0x54006a00 0x40>; 100 interrupts = <0 37 4>; 101 pinctrl-names = "default"; 102 pinctrl-0 = <&pinctrl_uart2>; 103 clocks = <&peri_clk 2>; 104 resets = <&peri_rst 2>; 105 }; 106 107 serial3: serial@54006b00 { 108 compatible = "socionext,uniphier-uart"; 109 status = "disabled"; 110 reg = <0x54006b00 0x40>; 111 interrupts = <0 177 4>; 112 pinctrl-names = "default"; 113 pinctrl-0 = <&pinctrl_uart3>; 114 clocks = <&peri_clk 3>; 115 resets = <&peri_rst 3>; 116 }; 117 118 gpio: gpio@55000000 { 119 compatible = "socionext,uniphier-gpio"; 120 reg = <0x55000000 0x200>; 121 interrupt-parent = <&aidet>; 122 interrupt-controller; 123 #interrupt-cells = <2>; 124 gpio-controller; 125 #gpio-cells = <2>; 126 gpio-ranges = <&pinctrl 0 0 0>; 127 gpio-ranges-group-names = "gpio_range"; 128 ngpios = <248>; 129 socionext,interrupt-ranges = <0 48 16>, <16 154 5>; 130 }; 131 132 i2c0: i2c@58780000 { 133 compatible = "socionext,uniphier-fi2c"; 134 status = "disabled"; 135 reg = <0x58780000 0x80>; 136 #address-cells = <1>; 137 #size-cells = <0>; 138 interrupts = <0 41 4>; 139 pinctrl-names = "default"; 140 pinctrl-0 = <&pinctrl_i2c0>; 141 clocks = <&peri_clk 4>; 142 resets = <&peri_rst 4>; 143 clock-frequency = <100000>; 144 }; 145 146 i2c1: i2c@58781000 { 147 compatible = "socionext,uniphier-fi2c"; 148 status = "disabled"; 149 reg = <0x58781000 0x80>; 150 #address-cells = <1>; 151 #size-cells = <0>; 152 interrupts = <0 42 4>; 153 pinctrl-names = "default"; 154 pinctrl-0 = <&pinctrl_i2c1>; 155 clocks = <&peri_clk 5>; 156 resets = <&peri_rst 5>; 157 clock-frequency = <100000>; 158 }; 159 160 i2c2: i2c@58782000 { 161 compatible = "socionext,uniphier-fi2c"; 162 status = "disabled"; 163 reg = <0x58782000 0x80>; 164 #address-cells = <1>; 165 #size-cells = <0>; 166 interrupts = <0 43 4>; 167 pinctrl-names = "default"; 168 pinctrl-0 = <&pinctrl_i2c2>; 169 clocks = <&peri_clk 6>; 170 resets = <&peri_rst 6>; 171 clock-frequency = <100000>; 172 }; 173 174 i2c3: i2c@58783000 { 175 compatible = "socionext,uniphier-fi2c"; 176 status = "disabled"; 177 reg = <0x58783000 0x80>; 178 #address-cells = <1>; 179 #size-cells = <0>; 180 interrupts = <0 44 4>; 181 pinctrl-names = "default"; 182 pinctrl-0 = <&pinctrl_i2c3>; 183 clocks = <&peri_clk 7>; 184 resets = <&peri_rst 7>; 185 clock-frequency = <100000>; 186 }; 187 188 /* i2c4 does not exist */ 189 190 /* chip-internal connection for DMD */ 191 i2c5: i2c@58785000 { 192 compatible = "socionext,uniphier-fi2c"; 193 reg = <0x58785000 0x80>; 194 #address-cells = <1>; 195 #size-cells = <0>; 196 interrupts = <0 25 4>; 197 clocks = <&peri_clk 9>; 198 resets = <&peri_rst 9>; 199 clock-frequency = <400000>; 200 }; 201 202 /* chip-internal connection for HDMI */ 203 i2c6: i2c@58786000 { 204 compatible = "socionext,uniphier-fi2c"; 205 reg = <0x58786000 0x80>; 206 #address-cells = <1>; 207 #size-cells = <0>; 208 interrupts = <0 26 4>; 209 clocks = <&peri_clk 10>; 210 resets = <&peri_rst 10>; 211 clock-frequency = <400000>; 212 }; 213 214 system_bus: system-bus@58c00000 { 215 compatible = "socionext,uniphier-system-bus"; 216 status = "disabled"; 217 reg = <0x58c00000 0x400>; 218 #address-cells = <2>; 219 #size-cells = <1>; 220 pinctrl-names = "default"; 221 pinctrl-0 = <&pinctrl_system_bus>; 222 }; 223 224 smpctrl@59801000 { 225 compatible = "socionext,uniphier-smpctrl"; 226 reg = <0x59801000 0x400>; 227 }; 228 229 mioctrl@59810000 { 230 compatible = "socionext,uniphier-pro4-mioctrl", 231 "simple-mfd", "syscon"; 232 reg = <0x59810000 0x800>; 233 234 mio_clk: clock { 235 compatible = "socionext,uniphier-pro4-mio-clock"; 236 #clock-cells = <1>; 237 }; 238 239 mio_rst: reset { 240 compatible = "socionext,uniphier-pro4-mio-reset"; 241 #reset-cells = <1>; 242 }; 243 }; 244 245 perictrl@59820000 { 246 compatible = "socionext,uniphier-pro4-perictrl", 247 "simple-mfd", "syscon"; 248 reg = <0x59820000 0x200>; 249 250 peri_clk: clock { 251 compatible = "socionext,uniphier-pro4-peri-clock"; 252 #clock-cells = <1>; 253 }; 254 255 peri_rst: reset { 256 compatible = "socionext,uniphier-pro4-peri-reset"; 257 #reset-cells = <1>; 258 }; 259 }; 260 261 sd: sdhc@5a400000 { 262 compatible = "socionext,uniphier-sdhc"; 263 status = "disabled"; 264 reg = <0x5a400000 0x200>; 265 interrupts = <0 76 4>; 266 pinctrl-names = "default", "1.8v"; 267 pinctrl-0 = <&pinctrl_sd>; 268 pinctrl-1 = <&pinctrl_sd_1v8>; 269 clocks = <&mio_clk 0>; 270 reset-names = "host", "bridge"; 271 resets = <&mio_rst 0>, <&mio_rst 3>; 272 bus-width = <4>; 273 cap-sd-highspeed; 274 sd-uhs-sdr12; 275 sd-uhs-sdr25; 276 sd-uhs-sdr50; 277 }; 278 279 emmc: sdhc@5a500000 { 280 compatible = "socionext,uniphier-sdhc"; 281 status = "disabled"; 282 reg = <0x5a500000 0x200>; 283 interrupts = <0 78 4>; 284 pinctrl-names = "default", "1.8v"; 285 pinctrl-0 = <&pinctrl_emmc>; 286 pinctrl-1 = <&pinctrl_emmc_1v8>; 287 clocks = <&mio_clk 1>; 288 reset-names = "host", "bridge"; 289 resets = <&mio_rst 1>, <&mio_rst 4>; 290 bus-width = <8>; 291 non-removable; 292 cap-mmc-highspeed; 293 cap-mmc-hw-reset; 294 }; 295 296 sd1: sdhc@5a600000 { 297 compatible = "socionext,uniphier-sdhc"; 298 status = "disabled"; 299 reg = <0x5a600000 0x200>; 300 interrupts = <0 85 4>; 301 pinctrl-names = "default", "1.8v"; 302 pinctrl-0 = <&pinctrl_sd1>; 303 pinctrl-1 = <&pinctrl_sd1_1v8>; 304 clocks = <&mio_clk 2>; 305 resets = <&mio_rst 2>, <&mio_rst 5>; 306 bus-width = <4>; 307 cap-sd-highspeed; 308 sd-uhs-sdr12; 309 sd-uhs-sdr25; 310 sd-uhs-sdr50; 311 }; 312 313 usb2: usb@5a800100 { 314 compatible = "socionext,uniphier-ehci", "generic-ehci"; 315 status = "disabled"; 316 reg = <0x5a800100 0x100>; 317 interrupts = <0 80 4>; 318 pinctrl-names = "default"; 319 pinctrl-0 = <&pinctrl_usb2>; 320 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, 321 <&mio_clk 12>; 322 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 323 <&mio_rst 12>; 324 has-transaction-translator; 325 }; 326 327 usb3: usb@5a810100 { 328 compatible = "socionext,uniphier-ehci", "generic-ehci"; 329 status = "disabled"; 330 reg = <0x5a810100 0x100>; 331 interrupts = <0 81 4>; 332 pinctrl-names = "default"; 333 pinctrl-0 = <&pinctrl_usb3>; 334 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, 335 <&mio_clk 13>; 336 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 337 <&mio_rst 13>; 338 has-transaction-translator; 339 }; 340 341 soc_glue: soc-glue@5f800000 { 342 compatible = "socionext,uniphier-pro4-soc-glue", 343 "simple-mfd", "syscon"; 344 reg = <0x5f800000 0x2000>; 345 346 pinctrl: pinctrl { 347 compatible = "socionext,uniphier-pro4-pinctrl"; 348 }; 349 }; 350 351 soc-glue@5f900000 { 352 compatible = "socionext,uniphier-pro4-soc-glue-debug", 353 "simple-mfd"; 354 #address-cells = <1>; 355 #size-cells = <1>; 356 ranges = <0 0x5f900000 0x2000>; 357 358 efuse@100 { 359 compatible = "socionext,uniphier-efuse"; 360 reg = <0x100 0x28>; 361 }; 362 363 efuse@130 { 364 compatible = "socionext,uniphier-efuse"; 365 reg = <0x130 0x8>; 366 }; 367 368 efuse@200 { 369 compatible = "socionext,uniphier-efuse"; 370 reg = <0x200 0x14>; 371 }; 372 }; 373 374 aidet: aidet@5fc20000 { 375 compatible = "socionext,uniphier-pro4-aidet"; 376 reg = <0x5fc20000 0x200>; 377 interrupt-controller; 378 #interrupt-cells = <2>; 379 }; 380 381 timer@60000200 { 382 compatible = "arm,cortex-a9-global-timer"; 383 reg = <0x60000200 0x20>; 384 interrupts = <1 11 0x304>; 385 clocks = <&arm_timer_clk>; 386 }; 387 388 timer@60000600 { 389 compatible = "arm,cortex-a9-twd-timer"; 390 reg = <0x60000600 0x20>; 391 interrupts = <1 13 0x304>; 392 clocks = <&arm_timer_clk>; 393 }; 394 395 intc: interrupt-controller@60001000 { 396 compatible = "arm,cortex-a9-gic"; 397 reg = <0x60001000 0x1000>, 398 <0x60000100 0x100>; 399 #interrupt-cells = <3>; 400 interrupt-controller; 401 }; 402 403 sysctrl@61840000 { 404 compatible = "socionext,uniphier-pro4-sysctrl", 405 "simple-mfd", "syscon"; 406 reg = <0x61840000 0x10000>; 407 408 sys_clk: clock { 409 compatible = "socionext,uniphier-pro4-clock"; 410 #clock-cells = <1>; 411 }; 412 413 sys_rst: reset { 414 compatible = "socionext,uniphier-pro4-reset"; 415 #reset-cells = <1>; 416 }; 417 }; 418 419 eth: ethernet@65000000 { 420 compatible = "socionext,uniphier-pro4-ave4"; 421 status = "disabled"; 422 reg = <0x65000000 0x8500>; 423 interrupts = <0 66 4>; 424 pinctrl-names = "default"; 425 pinctrl-0 = <&pinctrl_ether_rgmii>; 426 clock-names = "gio", "ether", "ether-gb", "ether-phy"; 427 clocks = <&sys_clk 12>, <&sys_clk 6>, <&sys_clk 7>, 428 <&sys_clk 10>; 429 reset-names = "gio", "ether"; 430 resets = <&sys_rst 12>, <&sys_rst 6>; 431 phy-mode = "rgmii"; 432 local-mac-address = [00 00 00 00 00 00]; 433 socionext,syscon-phy-mode = <&soc_glue 0>; 434 435 mdio: mdio { 436 #address-cells = <1>; 437 #size-cells = <0>; 438 }; 439 }; 440 441 usb0: usb@65b00000 { 442 compatible = "socionext,uniphier-pro4-dwc3"; 443 status = "disabled"; 444 reg = <0x65b00000 0x1000>; 445 #address-cells = <1>; 446 #size-cells = <1>; 447 ranges; 448 pinctrl-names = "default"; 449 pinctrl-0 = <&pinctrl_usb0>; 450 dwc3@65a00000 { 451 compatible = "snps,dwc3"; 452 reg = <0x65a00000 0x10000>; 453 interrupts = <0 134 4>; 454 dr_mode = "host"; 455 tx-fifo-resize; 456 }; 457 }; 458 459 usb1: usb@65d00000 { 460 compatible = "socionext,uniphier-pro4-dwc3"; 461 status = "disabled"; 462 reg = <0x65d00000 0x1000>; 463 #address-cells = <1>; 464 #size-cells = <1>; 465 ranges; 466 pinctrl-names = "default"; 467 pinctrl-0 = <&pinctrl_usb1>; 468 dwc3@65c00000 { 469 compatible = "snps,dwc3"; 470 reg = <0x65c00000 0x10000>; 471 interrupts = <0 137 4>; 472 dr_mode = "host"; 473 tx-fifo-resize; 474 }; 475 }; 476 477 nand: nand@68000000 { 478 compatible = "socionext,uniphier-denali-nand-v5a"; 479 status = "disabled"; 480 reg-names = "nand_data", "denali_reg"; 481 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 482 interrupts = <0 65 4>; 483 pinctrl-names = "default"; 484 pinctrl-0 = <&pinctrl_nand>; 485 clocks = <&sys_clk 2>; 486 resets = <&sys_rst 2>; 487 }; 488 }; 489}; 490 491#include "uniphier-pinctrl.dtsi" 492