1/* 2 * Device Tree Source for UniPhier Pro4 SoC 3 * 4 * Copyright (C) 2015-2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 */ 9 10#include <dt-bindings/gpio/uniphier-gpio.h> 11 12/ { 13 compatible = "socionext,uniphier-pro4"; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu@0 { 22 device_type = "cpu"; 23 compatible = "arm,cortex-a9"; 24 reg = <0>; 25 enable-method = "psci"; 26 next-level-cache = <&l2>; 27 }; 28 29 cpu@1 { 30 device_type = "cpu"; 31 compatible = "arm,cortex-a9"; 32 reg = <1>; 33 enable-method = "psci"; 34 next-level-cache = <&l2>; 35 }; 36 }; 37 38 psci { 39 compatible = "arm,psci-0.2"; 40 method = "smc"; 41 }; 42 43 clocks { 44 refclk: ref { 45 compatible = "fixed-clock"; 46 #clock-cells = <0>; 47 clock-frequency = <25000000>; 48 }; 49 50 arm_timer_clk: arm-timer { 51 #clock-cells = <0>; 52 compatible = "fixed-clock"; 53 clock-frequency = <50000000>; 54 }; 55 }; 56 57 soc { 58 compatible = "simple-bus"; 59 #address-cells = <1>; 60 #size-cells = <1>; 61 ranges; 62 interrupt-parent = <&intc>; 63 64 l2: l2-cache@500c0000 { 65 compatible = "socionext,uniphier-system-cache"; 66 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, 67 <0x506c0000 0x400>; 68 interrupts = <0 174 4>, <0 175 4>; 69 cache-unified; 70 cache-size = <(768 * 1024)>; 71 cache-sets = <256>; 72 cache-line-size = <128>; 73 cache-level = <2>; 74 }; 75 76 serial0: serial@54006800 { 77 compatible = "socionext,uniphier-uart"; 78 status = "disabled"; 79 reg = <0x54006800 0x40>; 80 interrupts = <0 33 4>; 81 pinctrl-names = "default"; 82 pinctrl-0 = <&pinctrl_uart0>; 83 clocks = <&peri_clk 0>; 84 clock-frequency = <73728000>; 85 resets = <&peri_rst 0>; 86 }; 87 88 serial1: serial@54006900 { 89 compatible = "socionext,uniphier-uart"; 90 status = "disabled"; 91 reg = <0x54006900 0x40>; 92 interrupts = <0 35 4>; 93 pinctrl-names = "default"; 94 pinctrl-0 = <&pinctrl_uart1>; 95 clocks = <&peri_clk 1>; 96 clock-frequency = <73728000>; 97 resets = <&peri_rst 1>; 98 }; 99 100 serial2: serial@54006a00 { 101 compatible = "socionext,uniphier-uart"; 102 status = "disabled"; 103 reg = <0x54006a00 0x40>; 104 interrupts = <0 37 4>; 105 pinctrl-names = "default"; 106 pinctrl-0 = <&pinctrl_uart2>; 107 clocks = <&peri_clk 2>; 108 clock-frequency = <73728000>; 109 resets = <&peri_rst 2>; 110 }; 111 112 serial3: serial@54006b00 { 113 compatible = "socionext,uniphier-uart"; 114 status = "disabled"; 115 reg = <0x54006b00 0x40>; 116 interrupts = <0 177 4>; 117 pinctrl-names = "default"; 118 pinctrl-0 = <&pinctrl_uart3>; 119 clocks = <&peri_clk 3>; 120 clock-frequency = <73728000>; 121 resets = <&peri_rst 3>; 122 }; 123 124 gpio: gpio@55000000 { 125 compatible = "socionext,uniphier-gpio"; 126 reg = <0x55000000 0x200>; 127 interrupt-parent = <&aidet>; 128 interrupt-controller; 129 #interrupt-cells = <2>; 130 gpio-controller; 131 #gpio-cells = <2>; 132 gpio-ranges = <&pinctrl 0 0 0>; 133 gpio-ranges-group-names = "gpio_range"; 134 ngpios = <248>; 135 socionext,interrupt-ranges = <0 48 16>, <16 154 5>; 136 }; 137 138 i2c0: i2c@58780000 { 139 compatible = "socionext,uniphier-fi2c"; 140 status = "disabled"; 141 reg = <0x58780000 0x80>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 interrupts = <0 41 4>; 145 pinctrl-names = "default"; 146 pinctrl-0 = <&pinctrl_i2c0>; 147 clocks = <&peri_clk 4>; 148 resets = <&peri_rst 4>; 149 clock-frequency = <100000>; 150 }; 151 152 i2c1: i2c@58781000 { 153 compatible = "socionext,uniphier-fi2c"; 154 status = "disabled"; 155 reg = <0x58781000 0x80>; 156 #address-cells = <1>; 157 #size-cells = <0>; 158 interrupts = <0 42 4>; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&pinctrl_i2c1>; 161 clocks = <&peri_clk 5>; 162 resets = <&peri_rst 5>; 163 clock-frequency = <100000>; 164 }; 165 166 i2c2: i2c@58782000 { 167 compatible = "socionext,uniphier-fi2c"; 168 status = "disabled"; 169 reg = <0x58782000 0x80>; 170 #address-cells = <1>; 171 #size-cells = <0>; 172 interrupts = <0 43 4>; 173 pinctrl-names = "default"; 174 pinctrl-0 = <&pinctrl_i2c2>; 175 clocks = <&peri_clk 6>; 176 resets = <&peri_rst 6>; 177 clock-frequency = <100000>; 178 }; 179 180 i2c3: i2c@58783000 { 181 compatible = "socionext,uniphier-fi2c"; 182 status = "disabled"; 183 reg = <0x58783000 0x80>; 184 #address-cells = <1>; 185 #size-cells = <0>; 186 interrupts = <0 44 4>; 187 pinctrl-names = "default"; 188 pinctrl-0 = <&pinctrl_i2c3>; 189 clocks = <&peri_clk 7>; 190 resets = <&peri_rst 7>; 191 clock-frequency = <100000>; 192 }; 193 194 /* i2c4 does not exist */ 195 196 /* chip-internal connection for DMD */ 197 i2c5: i2c@58785000 { 198 compatible = "socionext,uniphier-fi2c"; 199 reg = <0x58785000 0x80>; 200 #address-cells = <1>; 201 #size-cells = <0>; 202 interrupts = <0 25 4>; 203 clocks = <&peri_clk 9>; 204 resets = <&peri_rst 9>; 205 clock-frequency = <400000>; 206 }; 207 208 /* chip-internal connection for HDMI */ 209 i2c6: i2c@58786000 { 210 compatible = "socionext,uniphier-fi2c"; 211 reg = <0x58786000 0x80>; 212 #address-cells = <1>; 213 #size-cells = <0>; 214 interrupts = <0 26 4>; 215 clocks = <&peri_clk 10>; 216 resets = <&peri_rst 10>; 217 clock-frequency = <400000>; 218 }; 219 220 system_bus: system-bus@58c00000 { 221 compatible = "socionext,uniphier-system-bus"; 222 status = "disabled"; 223 reg = <0x58c00000 0x400>; 224 #address-cells = <2>; 225 #size-cells = <1>; 226 pinctrl-names = "default"; 227 pinctrl-0 = <&pinctrl_system_bus>; 228 }; 229 230 smpctrl@59801000 { 231 compatible = "socionext,uniphier-smpctrl"; 232 reg = <0x59801000 0x400>; 233 }; 234 235 mioctrl@59810000 { 236 compatible = "socionext,uniphier-pro4-mioctrl", 237 "simple-mfd", "syscon"; 238 reg = <0x59810000 0x800>; 239 240 mio_clk: clock { 241 compatible = "socionext,uniphier-pro4-mio-clock"; 242 #clock-cells = <1>; 243 }; 244 245 mio_rst: reset { 246 compatible = "socionext,uniphier-pro4-mio-reset"; 247 #reset-cells = <1>; 248 }; 249 }; 250 251 perictrl@59820000 { 252 compatible = "socionext,uniphier-pro4-perictrl", 253 "simple-mfd", "syscon"; 254 reg = <0x59820000 0x200>; 255 256 peri_clk: clock { 257 compatible = "socionext,uniphier-pro4-peri-clock"; 258 #clock-cells = <1>; 259 }; 260 261 peri_rst: reset { 262 compatible = "socionext,uniphier-pro4-peri-reset"; 263 #reset-cells = <1>; 264 }; 265 }; 266 267 sd: sdhc@5a400000 { 268 compatible = "socionext,uniphier-sdhc"; 269 status = "disabled"; 270 reg = <0x5a400000 0x200>; 271 interrupts = <0 76 4>; 272 pinctrl-names = "default", "1.8v"; 273 pinctrl-0 = <&pinctrl_sd>; 274 pinctrl-1 = <&pinctrl_sd_1v8>; 275 clocks = <&mio_clk 0>; 276 reset-names = "host", "bridge"; 277 resets = <&mio_rst 0>, <&mio_rst 3>; 278 bus-width = <4>; 279 cap-sd-highspeed; 280 sd-uhs-sdr12; 281 sd-uhs-sdr25; 282 sd-uhs-sdr50; 283 }; 284 285 emmc: sdhc@5a500000 { 286 compatible = "socionext,uniphier-sdhc"; 287 status = "disabled"; 288 reg = <0x5a500000 0x200>; 289 interrupts = <0 78 4>; 290 pinctrl-names = "default", "1.8v"; 291 pinctrl-0 = <&pinctrl_emmc>; 292 pinctrl-1 = <&pinctrl_emmc_1v8>; 293 clocks = <&mio_clk 1>; 294 reset-names = "host", "bridge"; 295 resets = <&mio_rst 1>, <&mio_rst 4>; 296 bus-width = <8>; 297 non-removable; 298 cap-mmc-highspeed; 299 cap-mmc-hw-reset; 300 }; 301 302 sd1: sdhc@5a600000 { 303 compatible = "socionext,uniphier-sdhc"; 304 status = "disabled"; 305 reg = <0x5a600000 0x200>; 306 interrupts = <0 85 4>; 307 pinctrl-names = "default", "1.8v"; 308 pinctrl-0 = <&pinctrl_sd1>; 309 pinctrl-1 = <&pinctrl_sd1_1v8>; 310 clocks = <&mio_clk 2>; 311 resets = <&mio_rst 2>, <&mio_rst 5>; 312 bus-width = <4>; 313 cap-sd-highspeed; 314 sd-uhs-sdr12; 315 sd-uhs-sdr25; 316 sd-uhs-sdr50; 317 }; 318 319 usb2: usb@5a800100 { 320 compatible = "socionext,uniphier-ehci", "generic-ehci"; 321 status = "disabled"; 322 reg = <0x5a800100 0x100>; 323 interrupts = <0 80 4>; 324 pinctrl-names = "default"; 325 pinctrl-0 = <&pinctrl_usb2>; 326 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, 327 <&mio_clk 12>; 328 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 329 <&mio_rst 12>; 330 has-transaction-translator; 331 }; 332 333 usb3: usb@5a810100 { 334 compatible = "socionext,uniphier-ehci", "generic-ehci"; 335 status = "disabled"; 336 reg = <0x5a810100 0x100>; 337 interrupts = <0 81 4>; 338 pinctrl-names = "default"; 339 pinctrl-0 = <&pinctrl_usb3>; 340 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, 341 <&mio_clk 13>; 342 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 343 <&mio_rst 13>; 344 has-transaction-translator; 345 }; 346 347 soc-glue@5f800000 { 348 compatible = "socionext,uniphier-pro4-soc-glue", 349 "simple-mfd", "syscon"; 350 reg = <0x5f800000 0x2000>; 351 352 pinctrl: pinctrl { 353 compatible = "socionext,uniphier-pro4-pinctrl"; 354 }; 355 }; 356 357 soc-glue@5f900000 { 358 compatible = "socionext,uniphier-pro4-soc-glue-debug", 359 "simple-mfd"; 360 #address-cells = <1>; 361 #size-cells = <1>; 362 ranges = <0 0x5f900000 0x2000>; 363 364 efuse@100 { 365 compatible = "socionext,uniphier-efuse"; 366 reg = <0x100 0x28>; 367 }; 368 369 efuse@130 { 370 compatible = "socionext,uniphier-efuse"; 371 reg = <0x130 0x8>; 372 }; 373 374 efuse@200 { 375 compatible = "socionext,uniphier-efuse"; 376 reg = <0x200 0x14>; 377 }; 378 }; 379 380 aidet: aidet@5fc20000 { 381 compatible = "socionext,uniphier-pro4-aidet"; 382 reg = <0x5fc20000 0x200>; 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 }; 386 387 timer@60000200 { 388 compatible = "arm,cortex-a9-global-timer"; 389 reg = <0x60000200 0x20>; 390 interrupts = <1 11 0x304>; 391 clocks = <&arm_timer_clk>; 392 }; 393 394 timer@60000600 { 395 compatible = "arm,cortex-a9-twd-timer"; 396 reg = <0x60000600 0x20>; 397 interrupts = <1 13 0x304>; 398 clocks = <&arm_timer_clk>; 399 }; 400 401 intc: interrupt-controller@60001000 { 402 compatible = "arm,cortex-a9-gic"; 403 reg = <0x60001000 0x1000>, 404 <0x60000100 0x100>; 405 #interrupt-cells = <3>; 406 interrupt-controller; 407 }; 408 409 sysctrl@61840000 { 410 compatible = "socionext,uniphier-pro4-sysctrl", 411 "simple-mfd", "syscon"; 412 reg = <0x61840000 0x10000>; 413 414 sys_clk: clock { 415 compatible = "socionext,uniphier-pro4-clock"; 416 #clock-cells = <1>; 417 }; 418 419 sys_rst: reset { 420 compatible = "socionext,uniphier-pro4-reset"; 421 #reset-cells = <1>; 422 }; 423 }; 424 425 usb0: usb@65b00000 { 426 compatible = "socionext,uniphier-pro4-dwc3"; 427 status = "disabled"; 428 reg = <0x65b00000 0x1000>; 429 #address-cells = <1>; 430 #size-cells = <1>; 431 ranges; 432 pinctrl-names = "default"; 433 pinctrl-0 = <&pinctrl_usb0>; 434 dwc3@65a00000 { 435 compatible = "snps,dwc3"; 436 reg = <0x65a00000 0x10000>; 437 interrupts = <0 134 4>; 438 dr_mode = "host"; 439 tx-fifo-resize; 440 }; 441 }; 442 443 usb1: usb@65d00000 { 444 compatible = "socionext,uniphier-pro4-dwc3"; 445 status = "disabled"; 446 reg = <0x65d00000 0x1000>; 447 #address-cells = <1>; 448 #size-cells = <1>; 449 ranges; 450 pinctrl-names = "default"; 451 pinctrl-0 = <&pinctrl_usb1>; 452 dwc3@65c00000 { 453 compatible = "snps,dwc3"; 454 reg = <0x65c00000 0x10000>; 455 interrupts = <0 137 4>; 456 dr_mode = "host"; 457 tx-fifo-resize; 458 }; 459 }; 460 461 nand: nand@68000000 { 462 compatible = "socionext,uniphier-denali-nand-v5a"; 463 status = "disabled"; 464 reg-names = "nand_data", "denali_reg"; 465 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 466 interrupts = <0 65 4>; 467 pinctrl-names = "default"; 468 pinctrl-0 = <&pinctrl_nand>; 469 clocks = <&sys_clk 2>; 470 resets = <&sys_rst 2>; 471 }; 472 }; 473}; 474 475#include "uniphier-pinctrl.dtsi" 476