1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Device Tree Source for UniPhier LD4 SoC 4// 5// Copyright (C) 2015-2016 Socionext Inc. 6// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 8#include <dt-bindings/gpio/uniphier-gpio.h> 9 10/ { 11 compatible = "socionext,uniphier-ld4"; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu@0 { 20 device_type = "cpu"; 21 compatible = "arm,cortex-a9"; 22 reg = <0>; 23 enable-method = "psci"; 24 next-level-cache = <&l2>; 25 }; 26 }; 27 28 psci { 29 compatible = "arm,psci-0.2"; 30 method = "smc"; 31 }; 32 33 clocks { 34 refclk: ref { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <24576000>; 38 }; 39 40 arm_timer_clk: arm-timer { 41 #clock-cells = <0>; 42 compatible = "fixed-clock"; 43 clock-frequency = <50000000>; 44 }; 45 }; 46 47 soc { 48 compatible = "simple-bus"; 49 #address-cells = <1>; 50 #size-cells = <1>; 51 ranges; 52 interrupt-parent = <&intc>; 53 54 l2: l2-cache@500c0000 { 55 compatible = "socionext,uniphier-system-cache"; 56 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, 57 <0x506c0000 0x400>; 58 interrupts = <0 174 4>, <0 175 4>; 59 cache-unified; 60 cache-size = <(512 * 1024)>; 61 cache-sets = <256>; 62 cache-line-size = <128>; 63 cache-level = <2>; 64 }; 65 66 serial0: serial@54006800 { 67 compatible = "socionext,uniphier-uart"; 68 status = "disabled"; 69 reg = <0x54006800 0x40>; 70 interrupts = <0 33 4>; 71 pinctrl-names = "default"; 72 pinctrl-0 = <&pinctrl_uart0>; 73 clocks = <&peri_clk 0>; 74 resets = <&peri_rst 0>; 75 }; 76 77 serial1: serial@54006900 { 78 compatible = "socionext,uniphier-uart"; 79 status = "disabled"; 80 reg = <0x54006900 0x40>; 81 interrupts = <0 35 4>; 82 pinctrl-names = "default"; 83 pinctrl-0 = <&pinctrl_uart1>; 84 clocks = <&peri_clk 1>; 85 resets = <&peri_rst 1>; 86 }; 87 88 serial2: serial@54006a00 { 89 compatible = "socionext,uniphier-uart"; 90 status = "disabled"; 91 reg = <0x54006a00 0x40>; 92 interrupts = <0 37 4>; 93 pinctrl-names = "default"; 94 pinctrl-0 = <&pinctrl_uart2>; 95 clocks = <&peri_clk 2>; 96 resets = <&peri_rst 2>; 97 }; 98 99 serial3: serial@54006b00 { 100 compatible = "socionext,uniphier-uart"; 101 status = "disabled"; 102 reg = <0x54006b00 0x40>; 103 interrupts = <0 29 4>; 104 pinctrl-names = "default"; 105 pinctrl-0 = <&pinctrl_uart3>; 106 clocks = <&peri_clk 3>; 107 resets = <&peri_rst 3>; 108 }; 109 110 gpio: gpio@55000000 { 111 compatible = "socionext,uniphier-gpio"; 112 reg = <0x55000000 0x200>; 113 interrupt-parent = <&aidet>; 114 interrupt-controller; 115 #interrupt-cells = <2>; 116 gpio-controller; 117 #gpio-cells = <2>; 118 gpio-ranges = <&pinctrl 0 0 0>; 119 gpio-ranges-group-names = "gpio_range"; 120 ngpios = <136>; 121 socionext,interrupt-ranges = <0 48 13>, <14 62 2>; 122 }; 123 124 i2c0: i2c@58400000 { 125 compatible = "socionext,uniphier-i2c"; 126 status = "disabled"; 127 reg = <0x58400000 0x40>; 128 #address-cells = <1>; 129 #size-cells = <0>; 130 interrupts = <0 41 1>; 131 pinctrl-names = "default"; 132 pinctrl-0 = <&pinctrl_i2c0>; 133 clocks = <&peri_clk 4>; 134 resets = <&peri_rst 4>; 135 clock-frequency = <100000>; 136 }; 137 138 i2c1: i2c@58480000 { 139 compatible = "socionext,uniphier-i2c"; 140 status = "disabled"; 141 reg = <0x58480000 0x40>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 interrupts = <0 42 1>; 145 pinctrl-names = "default"; 146 pinctrl-0 = <&pinctrl_i2c1>; 147 clocks = <&peri_clk 5>; 148 resets = <&peri_rst 5>; 149 clock-frequency = <100000>; 150 }; 151 152 /* chip-internal connection for DMD */ 153 i2c2: i2c@58500000 { 154 compatible = "socionext,uniphier-i2c"; 155 reg = <0x58500000 0x40>; 156 #address-cells = <1>; 157 #size-cells = <0>; 158 interrupts = <0 43 1>; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&pinctrl_i2c2>; 161 clocks = <&peri_clk 6>; 162 resets = <&peri_rst 6>; 163 clock-frequency = <400000>; 164 }; 165 166 i2c3: i2c@58580000 { 167 compatible = "socionext,uniphier-i2c"; 168 status = "disabled"; 169 reg = <0x58580000 0x40>; 170 #address-cells = <1>; 171 #size-cells = <0>; 172 interrupts = <0 44 1>; 173 pinctrl-names = "default"; 174 pinctrl-0 = <&pinctrl_i2c3>; 175 clocks = <&peri_clk 7>; 176 resets = <&peri_rst 7>; 177 clock-frequency = <100000>; 178 }; 179 180 system_bus: system-bus@58c00000 { 181 compatible = "socionext,uniphier-system-bus"; 182 status = "disabled"; 183 reg = <0x58c00000 0x400>; 184 #address-cells = <2>; 185 #size-cells = <1>; 186 pinctrl-names = "default"; 187 pinctrl-0 = <&pinctrl_system_bus>; 188 }; 189 190 smpctrl@59801000 { 191 compatible = "socionext,uniphier-smpctrl"; 192 reg = <0x59801000 0x400>; 193 }; 194 195 mioctrl@59810000 { 196 compatible = "socionext,uniphier-ld4-mioctrl", 197 "simple-mfd", "syscon"; 198 reg = <0x59810000 0x800>; 199 200 mio_clk: clock { 201 compatible = "socionext,uniphier-ld4-mio-clock"; 202 #clock-cells = <1>; 203 }; 204 205 mio_rst: reset { 206 compatible = "socionext,uniphier-ld4-mio-reset"; 207 #reset-cells = <1>; 208 }; 209 }; 210 211 perictrl@59820000 { 212 compatible = "socionext,uniphier-ld4-perictrl", 213 "simple-mfd", "syscon"; 214 reg = <0x59820000 0x200>; 215 216 peri_clk: clock { 217 compatible = "socionext,uniphier-ld4-peri-clock"; 218 #clock-cells = <1>; 219 }; 220 221 peri_rst: reset { 222 compatible = "socionext,uniphier-ld4-peri-reset"; 223 #reset-cells = <1>; 224 }; 225 }; 226 227 sd: sdhc@5a400000 { 228 compatible = "socionext,uniphier-sdhc"; 229 status = "disabled"; 230 reg = <0x5a400000 0x200>; 231 interrupts = <0 76 4>; 232 pinctrl-names = "default", "1.8v"; 233 pinctrl-0 = <&pinctrl_sd>; 234 pinctrl-1 = <&pinctrl_sd_1v8>; 235 clocks = <&mio_clk 0>; 236 reset-names = "host", "bridge"; 237 resets = <&mio_rst 0>, <&mio_rst 3>; 238 bus-width = <4>; 239 cap-sd-highspeed; 240 sd-uhs-sdr12; 241 sd-uhs-sdr25; 242 sd-uhs-sdr50; 243 }; 244 245 emmc: sdhc@5a500000 { 246 compatible = "socionext,uniphier-sdhc"; 247 status = "disabled"; 248 reg = <0x5a500000 0x200>; 249 interrupts = <0 78 4>; 250 pinctrl-names = "default", "1.8v"; 251 pinctrl-0 = <&pinctrl_emmc>; 252 pinctrl-1 = <&pinctrl_emmc_1v8>; 253 clocks = <&mio_clk 1>; 254 reset-names = "host", "bridge"; 255 resets = <&mio_rst 1>, <&mio_rst 4>; 256 bus-width = <8>; 257 non-removable; 258 cap-mmc-highspeed; 259 cap-mmc-hw-reset; 260 }; 261 262 usb0: usb@5a800100 { 263 compatible = "socionext,uniphier-ehci", "generic-ehci"; 264 status = "disabled"; 265 reg = <0x5a800100 0x100>; 266 interrupts = <0 80 4>; 267 pinctrl-names = "default"; 268 pinctrl-0 = <&pinctrl_usb0>; 269 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, 270 <&mio_clk 12>; 271 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 272 <&mio_rst 12>; 273 has-transaction-translator; 274 }; 275 276 usb1: usb@5a810100 { 277 compatible = "socionext,uniphier-ehci", "generic-ehci"; 278 status = "disabled"; 279 reg = <0x5a810100 0x100>; 280 interrupts = <0 81 4>; 281 pinctrl-names = "default"; 282 pinctrl-0 = <&pinctrl_usb1>; 283 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, 284 <&mio_clk 13>; 285 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 286 <&mio_rst 13>; 287 has-transaction-translator; 288 }; 289 290 usb2: usb@5a820100 { 291 compatible = "socionext,uniphier-ehci", "generic-ehci"; 292 status = "disabled"; 293 reg = <0x5a820100 0x100>; 294 interrupts = <0 82 4>; 295 pinctrl-names = "default"; 296 pinctrl-0 = <&pinctrl_usb2>; 297 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, 298 <&mio_clk 14>; 299 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, 300 <&mio_rst 14>; 301 has-transaction-translator; 302 }; 303 304 soc-glue@5f800000 { 305 compatible = "socionext,uniphier-ld4-soc-glue", 306 "simple-mfd", "syscon"; 307 reg = <0x5f800000 0x2000>; 308 309 pinctrl: pinctrl { 310 compatible = "socionext,uniphier-ld4-pinctrl"; 311 }; 312 }; 313 314 soc-glue@5f900000 { 315 compatible = "socionext,uniphier-ld4-soc-glue-debug", 316 "simple-mfd"; 317 #address-cells = <1>; 318 #size-cells = <1>; 319 ranges = <0 0x5f900000 0x2000>; 320 321 efuse@100 { 322 compatible = "socionext,uniphier-efuse"; 323 reg = <0x100 0x28>; 324 }; 325 326 efuse@130 { 327 compatible = "socionext,uniphier-efuse"; 328 reg = <0x130 0x8>; 329 }; 330 }; 331 332 timer@60000200 { 333 compatible = "arm,cortex-a9-global-timer"; 334 reg = <0x60000200 0x20>; 335 interrupts = <1 11 0x104>; 336 clocks = <&arm_timer_clk>; 337 }; 338 339 timer@60000600 { 340 compatible = "arm,cortex-a9-twd-timer"; 341 reg = <0x60000600 0x20>; 342 interrupts = <1 13 0x104>; 343 clocks = <&arm_timer_clk>; 344 }; 345 346 intc: interrupt-controller@60001000 { 347 compatible = "arm,cortex-a9-gic"; 348 reg = <0x60001000 0x1000>, 349 <0x60000100 0x100>; 350 #interrupt-cells = <3>; 351 interrupt-controller; 352 }; 353 354 aidet: aidet@61830000 { 355 compatible = "socionext,uniphier-ld4-aidet"; 356 reg = <0x61830000 0x200>; 357 interrupt-controller; 358 #interrupt-cells = <2>; 359 }; 360 361 sysctrl@61840000 { 362 compatible = "socionext,uniphier-ld4-sysctrl", 363 "simple-mfd", "syscon"; 364 reg = <0x61840000 0x10000>; 365 366 sys_clk: clock { 367 compatible = "socionext,uniphier-ld4-clock"; 368 #clock-cells = <1>; 369 }; 370 371 sys_rst: reset { 372 compatible = "socionext,uniphier-ld4-reset"; 373 #reset-cells = <1>; 374 }; 375 }; 376 377 nand: nand@68000000 { 378 compatible = "socionext,uniphier-denali-nand-v5a"; 379 status = "disabled"; 380 reg-names = "nand_data", "denali_reg"; 381 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 382 interrupts = <0 65 4>; 383 pinctrl-names = "default"; 384 pinctrl-0 = <&pinctrl_nand2cs>; 385 clocks = <&sys_clk 2>; 386 resets = <&sys_rst 2>; 387 }; 388 }; 389}; 390 391#include "uniphier-pinctrl.dtsi" 392