1/* 2 * Device Tree Source for UniPhier LD20 SoC 3 * 4 * Copyright (C) 2015-2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 */ 9 10/memreserve/ 0x80000000 0x02000000; 11 12/ { 13 compatible = "socionext,uniphier-ld20"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&gic>; 17 18 cpus { 19 #address-cells = <2>; 20 #size-cells = <0>; 21 22 cpu-map { 23 cluster0 { 24 core0 { 25 cpu = <&cpu0>; 26 }; 27 core1 { 28 cpu = <&cpu1>; 29 }; 30 }; 31 32 cluster1 { 33 core0 { 34 cpu = <&cpu2>; 35 }; 36 core1 { 37 cpu = <&cpu3>; 38 }; 39 }; 40 }; 41 42 cpu0: cpu@0 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a72", "arm,armv8"; 45 reg = <0 0x000>; 46 clocks = <&sys_clk 32>; 47 enable-method = "psci"; 48 operating-points-v2 = <&cluster0_opp>; 49 }; 50 51 cpu1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a72", "arm,armv8"; 54 reg = <0 0x001>; 55 clocks = <&sys_clk 32>; 56 enable-method = "psci"; 57 operating-points-v2 = <&cluster0_opp>; 58 }; 59 60 cpu2: cpu@100 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53", "arm,armv8"; 63 reg = <0 0x100>; 64 clocks = <&sys_clk 33>; 65 enable-method = "psci"; 66 operating-points-v2 = <&cluster1_opp>; 67 }; 68 69 cpu3: cpu@101 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53", "arm,armv8"; 72 reg = <0 0x101>; 73 clocks = <&sys_clk 33>; 74 enable-method = "psci"; 75 operating-points-v2 = <&cluster1_opp>; 76 }; 77 }; 78 79 cluster0_opp: opp_table0 { 80 compatible = "operating-points-v2"; 81 opp-shared; 82 83 opp-250000000 { 84 opp-hz = /bits/ 64 <250000000>; 85 clock-latency-ns = <300>; 86 }; 87 opp-275000000 { 88 opp-hz = /bits/ 64 <275000000>; 89 clock-latency-ns = <300>; 90 }; 91 opp-500000000 { 92 opp-hz = /bits/ 64 <500000000>; 93 clock-latency-ns = <300>; 94 }; 95 opp-550000000 { 96 opp-hz = /bits/ 64 <550000000>; 97 clock-latency-ns = <300>; 98 }; 99 opp-666667000 { 100 opp-hz = /bits/ 64 <666667000>; 101 clock-latency-ns = <300>; 102 }; 103 opp-733334000 { 104 opp-hz = /bits/ 64 <733334000>; 105 clock-latency-ns = <300>; 106 }; 107 opp-1000000000 { 108 opp-hz = /bits/ 64 <1000000000>; 109 clock-latency-ns = <300>; 110 }; 111 opp-1100000000 { 112 opp-hz = /bits/ 64 <1100000000>; 113 clock-latency-ns = <300>; 114 }; 115 }; 116 117 cluster1_opp: opp_table1 { 118 compatible = "operating-points-v2"; 119 opp-shared; 120 121 opp-250000000 { 122 opp-hz = /bits/ 64 <250000000>; 123 clock-latency-ns = <300>; 124 }; 125 opp-275000000 { 126 opp-hz = /bits/ 64 <275000000>; 127 clock-latency-ns = <300>; 128 }; 129 opp-500000000 { 130 opp-hz = /bits/ 64 <500000000>; 131 clock-latency-ns = <300>; 132 }; 133 opp-550000000 { 134 opp-hz = /bits/ 64 <550000000>; 135 clock-latency-ns = <300>; 136 }; 137 opp-666667000 { 138 opp-hz = /bits/ 64 <666667000>; 139 clock-latency-ns = <300>; 140 }; 141 opp-733334000 { 142 opp-hz = /bits/ 64 <733334000>; 143 clock-latency-ns = <300>; 144 }; 145 opp-1000000000 { 146 opp-hz = /bits/ 64 <1000000000>; 147 clock-latency-ns = <300>; 148 }; 149 opp-1100000000 { 150 opp-hz = /bits/ 64 <1100000000>; 151 clock-latency-ns = <300>; 152 }; 153 }; 154 155 psci { 156 compatible = "arm,psci-1.0"; 157 method = "smc"; 158 }; 159 160 clocks { 161 refclk: ref { 162 compatible = "fixed-clock"; 163 #clock-cells = <0>; 164 clock-frequency = <25000000>; 165 }; 166 }; 167 168 timer { 169 compatible = "arm,armv8-timer"; 170 interrupts = <1 13 4>, 171 <1 14 4>, 172 <1 11 4>, 173 <1 10 4>; 174 }; 175 176 soc@0 { 177 compatible = "simple-bus"; 178 #address-cells = <1>; 179 #size-cells = <1>; 180 ranges = <0 0 0 0xffffffff>; 181 182 serial0: serial@54006800 { 183 compatible = "socionext,uniphier-uart"; 184 status = "disabled"; 185 reg = <0x54006800 0x40>; 186 interrupts = <0 33 4>; 187 pinctrl-names = "default"; 188 pinctrl-0 = <&pinctrl_uart0>; 189 clocks = <&peri_clk 0>; 190 clock-frequency = <58820000>; 191 }; 192 193 serial1: serial@54006900 { 194 compatible = "socionext,uniphier-uart"; 195 status = "disabled"; 196 reg = <0x54006900 0x40>; 197 interrupts = <0 35 4>; 198 pinctrl-names = "default"; 199 pinctrl-0 = <&pinctrl_uart1>; 200 clocks = <&peri_clk 1>; 201 clock-frequency = <58820000>; 202 }; 203 204 serial2: serial@54006a00 { 205 compatible = "socionext,uniphier-uart"; 206 status = "disabled"; 207 reg = <0x54006a00 0x40>; 208 interrupts = <0 37 4>; 209 pinctrl-names = "default"; 210 pinctrl-0 = <&pinctrl_uart2>; 211 clocks = <&peri_clk 2>; 212 clock-frequency = <58820000>; 213 }; 214 215 serial3: serial@54006b00 { 216 compatible = "socionext,uniphier-uart"; 217 status = "disabled"; 218 reg = <0x54006b00 0x40>; 219 interrupts = <0 177 4>; 220 pinctrl-names = "default"; 221 pinctrl-0 = <&pinctrl_uart3>; 222 clocks = <&peri_clk 3>; 223 clock-frequency = <58820000>; 224 }; 225 226 i2c0: i2c@58780000 { 227 compatible = "socionext,uniphier-fi2c"; 228 status = "disabled"; 229 reg = <0x58780000 0x80>; 230 #address-cells = <1>; 231 #size-cells = <0>; 232 interrupts = <0 41 4>; 233 pinctrl-names = "default"; 234 pinctrl-0 = <&pinctrl_i2c0>; 235 clocks = <&peri_clk 4>; 236 clock-frequency = <100000>; 237 }; 238 239 i2c1: i2c@58781000 { 240 compatible = "socionext,uniphier-fi2c"; 241 status = "disabled"; 242 reg = <0x58781000 0x80>; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 interrupts = <0 42 4>; 246 pinctrl-names = "default"; 247 pinctrl-0 = <&pinctrl_i2c1>; 248 clocks = <&peri_clk 5>; 249 clock-frequency = <100000>; 250 }; 251 252 i2c2: i2c@58782000 { 253 compatible = "socionext,uniphier-fi2c"; 254 reg = <0x58782000 0x80>; 255 #address-cells = <1>; 256 #size-cells = <0>; 257 interrupts = <0 43 4>; 258 clocks = <&peri_clk 6>; 259 clock-frequency = <400000>; 260 }; 261 262 i2c3: i2c@58783000 { 263 compatible = "socionext,uniphier-fi2c"; 264 status = "disabled"; 265 reg = <0x58783000 0x80>; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 interrupts = <0 44 4>; 269 pinctrl-names = "default"; 270 pinctrl-0 = <&pinctrl_i2c3>; 271 clocks = <&peri_clk 7>; 272 clock-frequency = <100000>; 273 }; 274 275 i2c4: i2c@58784000 { 276 compatible = "socionext,uniphier-fi2c"; 277 status = "disabled"; 278 reg = <0x58784000 0x80>; 279 #address-cells = <1>; 280 #size-cells = <0>; 281 interrupts = <0 45 4>; 282 pinctrl-names = "default"; 283 pinctrl-0 = <&pinctrl_i2c4>; 284 clocks = <&peri_clk 8>; 285 clock-frequency = <100000>; 286 }; 287 288 i2c5: i2c@58785000 { 289 compatible = "socionext,uniphier-fi2c"; 290 reg = <0x58785000 0x80>; 291 #address-cells = <1>; 292 #size-cells = <0>; 293 interrupts = <0 25 4>; 294 clocks = <&peri_clk 9>; 295 clock-frequency = <400000>; 296 }; 297 298 system_bus: system-bus@58c00000 { 299 compatible = "socionext,uniphier-system-bus"; 300 status = "disabled"; 301 reg = <0x58c00000 0x400>; 302 #address-cells = <2>; 303 #size-cells = <1>; 304 pinctrl-names = "default"; 305 pinctrl-0 = <&pinctrl_system_bus>; 306 }; 307 308 smpctrl@59801000 { 309 compatible = "socionext,uniphier-smpctrl"; 310 reg = <0x59801000 0x400>; 311 }; 312 313 sdctrl@59810000 { 314 compatible = "socionext,uniphier-ld20-sdctrl", 315 "simple-mfd", "syscon"; 316 reg = <0x59810000 0x400>; 317 318 sd_clk: clock { 319 compatible = "socionext,uniphier-ld20-sd-clock"; 320 #clock-cells = <1>; 321 }; 322 323 sd_rst: reset { 324 compatible = "socionext,uniphier-ld20-sd-reset"; 325 #reset-cells = <1>; 326 }; 327 }; 328 329 perictrl@59820000 { 330 compatible = "socionext,uniphier-ld20-perictrl", 331 "simple-mfd", "syscon"; 332 reg = <0x59820000 0x200>; 333 334 peri_clk: clock { 335 compatible = "socionext,uniphier-ld20-peri-clock"; 336 #clock-cells = <1>; 337 }; 338 339 peri_rst: reset { 340 compatible = "socionext,uniphier-ld20-peri-reset"; 341 #reset-cells = <1>; 342 }; 343 }; 344 345 emmc: sdhc@5a000000 { 346 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 347 reg = <0x5a000000 0x400>; 348 interrupts = <0 78 4>; 349 pinctrl-names = "default"; 350 pinctrl-0 = <&pinctrl_emmc_1v8>; 351 clocks = <&sys_clk 4>; 352 bus-width = <8>; 353 mmc-ddr-1_8v; 354 mmc-hs200-1_8v; 355 cdns,phy-input-delay-legacy = <4>; 356 cdns,phy-input-delay-mmc-highspeed = <2>; 357 cdns,phy-input-delay-mmc-ddr = <3>; 358 cdns,phy-dll-delay-sdclk = <21>; 359 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 360 }; 361 362 sd: sdhc@5a400000 { 363 compatible = "socionext,uniphier-sdhc"; 364 status = "disabled"; 365 reg = <0x5a400000 0x800>; 366 interrupts = <0 76 4>; 367 pinctrl-names = "default"; 368 pinctrl-0 = <&pinctrl_sd>; 369 clocks = <&sd_clk 0>; 370 reset-names = "host"; 371 resets = <&sd_rst 0>; 372 bus-width = <4>; 373 cap-sd-highspeed; 374 }; 375 376 soc-glue@5f800000 { 377 compatible = "socionext,uniphier-ld20-soc-glue", 378 "simple-mfd", "syscon"; 379 reg = <0x5f800000 0x2000>; 380 381 pinctrl: pinctrl { 382 compatible = "socionext,uniphier-ld20-pinctrl"; 383 }; 384 }; 385 386 aidet: aidet@5fc20000 { 387 compatible = "socionext,uniphier-ld20-aidet"; 388 reg = <0x5fc20000 0x200>; 389 interrupt-controller; 390 #interrupt-cells = <2>; 391 }; 392 393 gic: interrupt-controller@5fe00000 { 394 compatible = "arm,gic-v3"; 395 reg = <0x5fe00000 0x10000>, /* GICD */ 396 <0x5fe80000 0x80000>; /* GICR */ 397 interrupt-controller; 398 #interrupt-cells = <3>; 399 interrupts = <1 9 4>; 400 }; 401 402 sysctrl@61840000 { 403 compatible = "socionext,uniphier-ld20-sysctrl", 404 "simple-mfd", "syscon"; 405 reg = <0x61840000 0x10000>; 406 407 sys_clk: clock { 408 compatible = "socionext,uniphier-ld20-clock"; 409 #clock-cells = <1>; 410 }; 411 412 sys_rst: reset { 413 compatible = "socionext,uniphier-ld20-reset"; 414 #reset-cells = <1>; 415 }; 416 417 watchdog { 418 compatible = "socionext,uniphier-wdt"; 419 }; 420 }; 421 422 usb: usb@65b00000 { 423 compatible = "socionext,uniphier-ld20-dwc3"; 424 reg = <0x65b00000 0x1000>; 425 #address-cells = <1>; 426 #size-cells = <1>; 427 ranges; 428 pinctrl-names = "default"; 429 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>, 430 <&pinctrl_usb2>, <&pinctrl_usb3>; 431 dwc3@65a00000 { 432 compatible = "snps,dwc3"; 433 reg = <0x65a00000 0x10000>; 434 interrupts = <0 134 4>; 435 dr_mode = "host"; 436 tx-fifo-resize; 437 }; 438 }; 439 440 nand: nand@68000000 { 441 compatible = "socionext,uniphier-denali-nand-v5b"; 442 status = "disabled"; 443 reg-names = "nand_data", "denali_reg"; 444 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 445 interrupts = <0 65 4>; 446 pinctrl-names = "default"; 447 pinctrl-0 = <&pinctrl_nand>; 448 clocks = <&sys_clk 2>; 449 }; 450 }; 451}; 452 453#include "uniphier-pinctrl.dtsi" 454