1/* 2 * Device Tree Source for UniPhier LD20 SoC 3 * 4 * Copyright (C) 2015-2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * This file is dual-licensed: you can use it either under the terms 8 * of the GPL or the X11 license, at your option. Note that this dual 9 * licensing only applies to this file, and not this project as a 10 * whole. 11 * 12 * a) This file is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of the 15 * License, or (at your option) any later version. 16 * 17 * This file is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * Or, alternatively, 23 * 24 * b) Permission is hereby granted, free of charge, to any person 25 * obtaining a copy of this software and associated documentation 26 * files (the "Software"), to deal in the Software without 27 * restriction, including without limitation the rights to use, 28 * copy, modify, merge, publish, distribute, sublicense, and/or 29 * sell copies of the Software, and to permit persons to whom the 30 * Software is furnished to do so, subject to the following 31 * conditions: 32 * 33 * The above copyright notice and this permission notice shall be 34 * included in all copies or substantial portions of the Software. 35 * 36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 43 * OTHER DEALINGS IN THE SOFTWARE. 44 */ 45 46/memreserve/ 0x80000000 0x00080000; 47 48/ { 49 compatible = "socionext,uniphier-ld20"; 50 #address-cells = <2>; 51 #size-cells = <2>; 52 interrupt-parent = <&gic>; 53 54 cpus { 55 #address-cells = <2>; 56 #size-cells = <0>; 57 58 cpu-map { 59 cluster0 { 60 core0 { 61 cpu = <&cpu0>; 62 }; 63 core1 { 64 cpu = <&cpu1>; 65 }; 66 }; 67 68 cluster1 { 69 core0 { 70 cpu = <&cpu2>; 71 }; 72 core1 { 73 cpu = <&cpu3>; 74 }; 75 }; 76 }; 77 78 cpu0: cpu@0 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a72", "arm,armv8"; 81 reg = <0 0x000>; 82 clocks = <&sys_clk 32>; 83 enable-method = "psci"; 84 operating-points-v2 = <&cluster0_opp>; 85 }; 86 87 cpu1: cpu@1 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a72", "arm,armv8"; 90 reg = <0 0x001>; 91 clocks = <&sys_clk 32>; 92 enable-method = "psci"; 93 operating-points-v2 = <&cluster0_opp>; 94 }; 95 96 cpu2: cpu@100 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a53", "arm,armv8"; 99 reg = <0 0x100>; 100 clocks = <&sys_clk 33>; 101 enable-method = "psci"; 102 operating-points-v2 = <&cluster1_opp>; 103 }; 104 105 cpu3: cpu@101 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53", "arm,armv8"; 108 reg = <0 0x101>; 109 clocks = <&sys_clk 33>; 110 enable-method = "psci"; 111 operating-points-v2 = <&cluster1_opp>; 112 }; 113 }; 114 115 cluster0_opp: opp_table0 { 116 compatible = "operating-points-v2"; 117 opp-shared; 118 119 opp-250000000 { 120 opp-hz = /bits/ 64 <250000000>; 121 clock-latency-ns = <300>; 122 }; 123 opp-275000000 { 124 opp-hz = /bits/ 64 <275000000>; 125 clock-latency-ns = <300>; 126 }; 127 opp-500000000 { 128 opp-hz = /bits/ 64 <500000000>; 129 clock-latency-ns = <300>; 130 }; 131 opp-550000000 { 132 opp-hz = /bits/ 64 <550000000>; 133 clock-latency-ns = <300>; 134 }; 135 opp-666667000 { 136 opp-hz = /bits/ 64 <666667000>; 137 clock-latency-ns = <300>; 138 }; 139 opp-733334000 { 140 opp-hz = /bits/ 64 <733334000>; 141 clock-latency-ns = <300>; 142 }; 143 opp-1000000000 { 144 opp-hz = /bits/ 64 <1000000000>; 145 clock-latency-ns = <300>; 146 }; 147 opp-1100000000 { 148 opp-hz = /bits/ 64 <1100000000>; 149 clock-latency-ns = <300>; 150 }; 151 }; 152 153 cluster1_opp: opp_table1 { 154 compatible = "operating-points-v2"; 155 opp-shared; 156 157 opp-250000000 { 158 opp-hz = /bits/ 64 <250000000>; 159 clock-latency-ns = <300>; 160 }; 161 opp-275000000 { 162 opp-hz = /bits/ 64 <275000000>; 163 clock-latency-ns = <300>; 164 }; 165 opp-500000000 { 166 opp-hz = /bits/ 64 <500000000>; 167 clock-latency-ns = <300>; 168 }; 169 opp-550000000 { 170 opp-hz = /bits/ 64 <550000000>; 171 clock-latency-ns = <300>; 172 }; 173 opp-666667000 { 174 opp-hz = /bits/ 64 <666667000>; 175 clock-latency-ns = <300>; 176 }; 177 opp-733334000 { 178 opp-hz = /bits/ 64 <733334000>; 179 clock-latency-ns = <300>; 180 }; 181 opp-1000000000 { 182 opp-hz = /bits/ 64 <1000000000>; 183 clock-latency-ns = <300>; 184 }; 185 opp-1100000000 { 186 opp-hz = /bits/ 64 <1100000000>; 187 clock-latency-ns = <300>; 188 }; 189 }; 190 191 psci { 192 compatible = "arm,psci-1.0"; 193 method = "smc"; 194 }; 195 196 clocks { 197 refclk: ref { 198 compatible = "fixed-clock"; 199 #clock-cells = <0>; 200 clock-frequency = <25000000>; 201 }; 202 }; 203 204 timer { 205 compatible = "arm,armv8-timer"; 206 interrupts = <1 13 4>, 207 <1 14 4>, 208 <1 11 4>, 209 <1 10 4>; 210 }; 211 212 soc@0 { 213 compatible = "simple-bus"; 214 #address-cells = <1>; 215 #size-cells = <1>; 216 ranges = <0 0 0 0xffffffff>; 217 u-boot,dm-pre-reloc; 218 219 serial0: serial@54006800 { 220 compatible = "socionext,uniphier-uart"; 221 status = "disabled"; 222 reg = <0x54006800 0x40>; 223 interrupts = <0 33 4>; 224 pinctrl-names = "default"; 225 pinctrl-0 = <&pinctrl_uart0>; 226 clocks = <&peri_clk 0>; 227 clock-frequency = <58820000>; 228 }; 229 230 serial1: serial@54006900 { 231 compatible = "socionext,uniphier-uart"; 232 status = "disabled"; 233 reg = <0x54006900 0x40>; 234 interrupts = <0 35 4>; 235 pinctrl-names = "default"; 236 pinctrl-0 = <&pinctrl_uart1>; 237 clocks = <&peri_clk 1>; 238 clock-frequency = <58820000>; 239 }; 240 241 serial2: serial@54006a00 { 242 compatible = "socionext,uniphier-uart"; 243 status = "disabled"; 244 reg = <0x54006a00 0x40>; 245 interrupts = <0 37 4>; 246 pinctrl-names = "default"; 247 pinctrl-0 = <&pinctrl_uart2>; 248 clocks = <&peri_clk 2>; 249 clock-frequency = <58820000>; 250 }; 251 252 serial3: serial@54006b00 { 253 compatible = "socionext,uniphier-uart"; 254 status = "disabled"; 255 reg = <0x54006b00 0x40>; 256 interrupts = <0 177 4>; 257 pinctrl-names = "default"; 258 pinctrl-0 = <&pinctrl_uart3>; 259 clocks = <&peri_clk 3>; 260 clock-frequency = <58820000>; 261 }; 262 263 i2c0: i2c@58780000 { 264 compatible = "socionext,uniphier-fi2c"; 265 status = "disabled"; 266 reg = <0x58780000 0x80>; 267 #address-cells = <1>; 268 #size-cells = <0>; 269 interrupts = <0 41 4>; 270 pinctrl-names = "default"; 271 pinctrl-0 = <&pinctrl_i2c0>; 272 clocks = <&peri_clk 4>; 273 clock-frequency = <100000>; 274 }; 275 276 i2c1: i2c@58781000 { 277 compatible = "socionext,uniphier-fi2c"; 278 status = "disabled"; 279 reg = <0x58781000 0x80>; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 interrupts = <0 42 4>; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&pinctrl_i2c1>; 285 clocks = <&peri_clk 5>; 286 clock-frequency = <100000>; 287 }; 288 289 i2c2: i2c@58782000 { 290 compatible = "socionext,uniphier-fi2c"; 291 reg = <0x58782000 0x80>; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 interrupts = <0 43 4>; 295 clocks = <&peri_clk 6>; 296 clock-frequency = <400000>; 297 }; 298 299 i2c3: i2c@58783000 { 300 compatible = "socionext,uniphier-fi2c"; 301 status = "disabled"; 302 reg = <0x58783000 0x80>; 303 #address-cells = <1>; 304 #size-cells = <0>; 305 interrupts = <0 44 4>; 306 pinctrl-names = "default"; 307 pinctrl-0 = <&pinctrl_i2c3>; 308 clocks = <&peri_clk 7>; 309 clock-frequency = <100000>; 310 }; 311 312 i2c4: i2c@58784000 { 313 compatible = "socionext,uniphier-fi2c"; 314 status = "disabled"; 315 reg = <0x58784000 0x80>; 316 #address-cells = <1>; 317 #size-cells = <0>; 318 interrupts = <0 45 4>; 319 pinctrl-names = "default"; 320 pinctrl-0 = <&pinctrl_i2c4>; 321 clocks = <&peri_clk 8>; 322 clock-frequency = <100000>; 323 }; 324 325 i2c5: i2c@58785000 { 326 compatible = "socionext,uniphier-fi2c"; 327 reg = <0x58785000 0x80>; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 interrupts = <0 25 4>; 331 clocks = <&peri_clk 9>; 332 clock-frequency = <400000>; 333 }; 334 335 system_bus: system-bus@58c00000 { 336 compatible = "socionext,uniphier-system-bus"; 337 status = "disabled"; 338 reg = <0x58c00000 0x400>; 339 #address-cells = <2>; 340 #size-cells = <1>; 341 pinctrl-names = "default"; 342 pinctrl-0 = <&pinctrl_system_bus>; 343 }; 344 345 smpctrl@59801000 { 346 compatible = "socionext,uniphier-smpctrl"; 347 reg = <0x59801000 0x400>; 348 }; 349 350 sdctrl@59810000 { 351 compatible = "socionext,uniphier-ld20-sdctrl", 352 "simple-mfd", "syscon"; 353 reg = <0x59810000 0x800>; 354 355 sd_clk: clock { 356 compatible = "socionext,uniphier-ld20-sd-clock"; 357 #clock-cells = <1>; 358 }; 359 360 sd_rst: reset { 361 compatible = "socionext,uniphier-ld20-sd-reset"; 362 #reset-cells = <1>; 363 }; 364 }; 365 366 perictrl@59820000 { 367 compatible = "socionext,uniphier-ld20-perictrl", 368 "simple-mfd", "syscon"; 369 reg = <0x59820000 0x200>; 370 371 peri_clk: clock { 372 compatible = "socionext,uniphier-ld20-peri-clock"; 373 #clock-cells = <1>; 374 }; 375 376 peri_rst: reset { 377 compatible = "socionext,uniphier-ld20-peri-reset"; 378 #reset-cells = <1>; 379 }; 380 }; 381 382 emmc: sdhc@5a000000 { 383 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 384 reg = <0x5a000000 0x400>; 385 interrupts = <0 78 4>; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&pinctrl_emmc_1v8>; 388 clocks = <&sys_clk 4>; 389 bus-width = <8>; 390 mmc-ddr-1_8v; 391 mmc-hs200-1_8v; 392 cdns,phy-input-delay-legacy = <4>; 393 cdns,phy-input-delay-mmc-highspeed = <2>; 394 cdns,phy-input-delay-mmc-ddr = <3>; 395 cdns,phy-dll-delay-sdclk = <21>; 396 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 397 }; 398 399 sd: sdhc@5a400000 { 400 compatible = "socionext,uniphier-sdhc"; 401 status = "disabled"; 402 reg = <0x5a400000 0x800>; 403 interrupts = <0 76 4>; 404 pinctrl-names = "default"; 405 pinctrl-0 = <&pinctrl_sd>; 406 clocks = <&sd_clk 0>; 407 reset-names = "host"; 408 resets = <&sd_rst 0>; 409 bus-width = <4>; 410 cap-sd-highspeed; 411 }; 412 413 soc-glue@5f800000 { 414 compatible = "socionext,uniphier-ld20-soc-glue", 415 "simple-mfd", "syscon"; 416 reg = <0x5f800000 0x2000>; 417 u-boot,dm-pre-reloc; 418 419 pinctrl: pinctrl { 420 compatible = "socionext,uniphier-ld20-pinctrl"; 421 u-boot,dm-pre-reloc; 422 }; 423 }; 424 425 aidet@5fc20000 { 426 compatible = "simple-mfd", "syscon"; 427 reg = <0x5fc20000 0x200>; 428 }; 429 430 gic: interrupt-controller@5fe00000 { 431 compatible = "arm,gic-v3"; 432 reg = <0x5fe00000 0x10000>, /* GICD */ 433 <0x5fe80000 0x80000>; /* GICR */ 434 interrupt-controller; 435 #interrupt-cells = <3>; 436 interrupts = <1 9 4>; 437 }; 438 439 sysctrl@61840000 { 440 compatible = "socionext,uniphier-ld20-sysctrl", 441 "simple-mfd", "syscon"; 442 reg = <0x61840000 0x10000>; 443 444 sys_clk: clock { 445 compatible = "socionext,uniphier-ld20-clock"; 446 #clock-cells = <1>; 447 }; 448 449 sys_rst: reset { 450 compatible = "socionext,uniphier-ld20-reset"; 451 #reset-cells = <1>; 452 }; 453 }; 454 455 usb: usb@65b00000 { 456 compatible = "socionext,uniphier-ld20-dwc3"; 457 reg = <0x65b00000 0x1000>; 458 #address-cells = <1>; 459 #size-cells = <1>; 460 ranges; 461 pinctrl-names = "default"; 462 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>, 463 <&pinctrl_usb2>, <&pinctrl_usb3>; 464 dwc3@65a00000 { 465 compatible = "snps,dwc3"; 466 reg = <0x65a00000 0x10000>; 467 interrupts = <0 134 4>; 468 tx-fifo-resize; 469 }; 470 }; 471 472 nand: nand@68000000 { 473 compatible = "socionext,uniphier-denali-nand-v5b"; 474 status = "disabled"; 475 reg-names = "nand_data", "denali_reg"; 476 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 477 interrupts = <0 65 4>; 478 pinctrl-names = "default"; 479 pinctrl-0 = <&pinctrl_nand>; 480 clocks = <&sys_clk 2>; 481 nand-ecc-strength = <8>; 482 }; 483 }; 484}; 485 486/include/ "uniphier-pinctrl.dtsi" 487