xref: /openbmc/u-boot/arch/arm/dts/uniphier-ld20.dtsi (revision 72c10153) 
1/*
2 * Device Tree Source for UniPhier LD20 SoC
3 *
4 * Copyright (C) 2015-2016 Socionext Inc.
5 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 *
7 * SPDX-License-Identifier:	GPL-2.0+	X11
8 */
9
10/memreserve/ 0x80000000 0x00000008;	/* cpu-release-addr */
11
12/ {
13	compatible = "socionext,uniphier-ld20";
14	#address-cells = <2>;
15	#size-cells = <2>;
16	interrupt-parent = <&gic>;
17
18	cpus {
19		#address-cells = <2>;
20		#size-cells = <0>;
21
22		cpu-map {
23			cluster0 {
24				core0 {
25					cpu = <&cpu0>;
26				};
27				core1 {
28					cpu = <&cpu1>;
29				};
30			};
31
32			cluster1 {
33				core0 {
34					cpu = <&cpu2>;
35				};
36				core1 {
37					cpu = <&cpu3>;
38				};
39			};
40		};
41
42		cpu0: cpu@0 {
43			device_type = "cpu";
44			compatible = "arm,cortex-a72", "arm,armv8";
45			reg = <0 0x000>;
46			enable-method = "spin-table";
47			cpu-release-addr = <0 0x80000000>;
48		};
49
50		cpu1: cpu@1 {
51			device_type = "cpu";
52			compatible = "arm,cortex-a72", "arm,armv8";
53			reg = <0 0x001>;
54			enable-method = "spin-table";
55			cpu-release-addr = <0 0x80000000>;
56		};
57
58		cpu2: cpu@100 {
59			device_type = "cpu";
60			compatible = "arm,cortex-a53", "arm,armv8";
61			reg = <0 0x100>;
62			enable-method = "spin-table";
63			cpu-release-addr = <0 0x80000000>;
64		};
65
66		cpu3: cpu@101 {
67			device_type = "cpu";
68			compatible = "arm,cortex-a53", "arm,armv8";
69			reg = <0 0x101>;
70			enable-method = "spin-table";
71			cpu-release-addr = <0 0x80000000>;
72		};
73	};
74
75	clocks {
76		refclk: ref {
77			compatible = "fixed-clock";
78			#clock-cells = <0>;
79			clock-frequency = <25000000>;
80		};
81
82		i2c_clk: i2c_clk {
83			#clock-cells = <0>;
84			compatible = "fixed-clock";
85			clock-frequency = <50000000>;
86		};
87	};
88
89	timer {
90		compatible = "arm,armv8-timer";
91		interrupts = <1 13 4>,
92			     <1 14 4>,
93			     <1 11 4>,
94			     <1 10 4>;
95	};
96
97	soc {
98		compatible = "simple-bus";
99		#address-cells = <1>;
100		#size-cells = <1>;
101		ranges = <0 0 0 0xffffffff>;
102		u-boot,dm-pre-reloc;
103
104		serial0: serial@54006800 {
105			compatible = "socionext,uniphier-uart";
106			status = "disabled";
107			reg = <0x54006800 0x40>;
108			interrupts = <0 33 4>;
109			pinctrl-names = "default";
110			pinctrl-0 = <&pinctrl_uart0>;
111			clocks = <&peri_clk 0>;
112			clock-frequency = <58820000>;
113		};
114
115		serial1: serial@54006900 {
116			compatible = "socionext,uniphier-uart";
117			status = "disabled";
118			reg = <0x54006900 0x40>;
119			interrupts = <0 35 4>;
120			pinctrl-names = "default";
121			pinctrl-0 = <&pinctrl_uart1>;
122			clocks = <&peri_clk 1>;
123			clock-frequency = <58820000>;
124		};
125
126		serial2: serial@54006a00 {
127			compatible = "socionext,uniphier-uart";
128			status = "disabled";
129			reg = <0x54006a00 0x40>;
130			interrupts = <0 37 4>;
131			pinctrl-names = "default";
132			pinctrl-0 = <&pinctrl_uart2>;
133			clocks = <&peri_clk 2>;
134			clock-frequency = <58820000>;
135		};
136
137		serial3: serial@54006b00 {
138			compatible = "socionext,uniphier-uart";
139			status = "disabled";
140			reg = <0x54006b00 0x40>;
141			interrupts = <0 177 4>;
142			pinctrl-names = "default";
143			pinctrl-0 = <&pinctrl_uart3>;
144			clocks = <&peri_clk 3>;
145			clock-frequency = <58820000>;
146		};
147
148		i2c0: i2c@58780000 {
149			compatible = "socionext,uniphier-fi2c";
150			status = "disabled";
151			reg = <0x58780000 0x80>;
152			#address-cells = <1>;
153			#size-cells = <0>;
154			interrupts = <0 41 4>;
155			pinctrl-names = "default";
156			pinctrl-0 = <&pinctrl_i2c0>;
157			clocks = <&i2c_clk>;
158			clock-frequency = <100000>;
159		};
160
161		i2c1: i2c@58781000 {
162			compatible = "socionext,uniphier-fi2c";
163			status = "disabled";
164			reg = <0x58781000 0x80>;
165			#address-cells = <1>;
166			#size-cells = <0>;
167			interrupts = <0 42 4>;
168			pinctrl-names = "default";
169			pinctrl-0 = <&pinctrl_i2c1>;
170			clocks = <&i2c_clk>;
171			clock-frequency = <100000>;
172		};
173
174		i2c2: i2c@58782000 {
175			compatible = "socionext,uniphier-fi2c";
176			reg = <0x58782000 0x80>;
177			#address-cells = <1>;
178			#size-cells = <0>;
179			interrupts = <0 43 4>;
180			clocks = <&i2c_clk>;
181			clock-frequency = <400000>;
182		};
183
184		i2c3: i2c@58783000 {
185			compatible = "socionext,uniphier-fi2c";
186			status = "disabled";
187			reg = <0x58783000 0x80>;
188			#address-cells = <1>;
189			#size-cells = <0>;
190			interrupts = <0 44 4>;
191			pinctrl-names = "default";
192			pinctrl-0 = <&pinctrl_i2c3>;
193			clocks = <&i2c_clk>;
194			clock-frequency = <100000>;
195		};
196
197		i2c4: i2c@58784000 {
198			compatible = "socionext,uniphier-fi2c";
199			status = "disabled";
200			reg = <0x58784000 0x80>;
201			#address-cells = <1>;
202			#size-cells = <0>;
203			interrupts = <0 45 4>;
204			pinctrl-names = "default";
205			pinctrl-0 = <&pinctrl_i2c4>;
206			clocks = <&i2c_clk>;
207			clock-frequency = <100000>;
208		};
209
210		i2c5: i2c@58785000 {
211			compatible = "socionext,uniphier-fi2c";
212			reg = <0x58785000 0x80>;
213			#address-cells = <1>;
214			#size-cells = <0>;
215			interrupts = <0 25 4>;
216			clocks = <&i2c_clk>;
217			clock-frequency = <400000>;
218		};
219
220		system_bus: system-bus@58c00000 {
221			compatible = "socionext,uniphier-system-bus";
222			status = "disabled";
223			reg = <0x58c00000 0x400>;
224			#address-cells = <2>;
225			#size-cells = <1>;
226			pinctrl-names = "default";
227			pinctrl-0 = <&pinctrl_system_bus>;
228		};
229
230		smpctrl@59800000 {
231			compatible = "socionext,uniphier-smpctrl";
232			reg = <0x59801000 0x400>;
233		};
234
235		mioctrl@59810000 {
236			compatible = "socionext,uniphier-mioctrl",
237				     "simple-mfd", "syscon";
238			reg = <0x59810000 0x800>;
239
240			mio_clk: clock {
241				compatible = "socionext,uniphier-ld20-mio-clock";
242				#clock-cells = <1>;
243			};
244
245			mio_rst: reset {
246				compatible = "socionext,uniphier-ld20-mio-reset";
247				#reset-cells = <1>;
248			};
249		};
250
251		perictrl@59820000 {
252			compatible = "socionext,uniphier-perictrl",
253				     "simple-mfd", "syscon";
254			reg = <0x59820000 0x200>;
255
256			peri_clk: clock {
257				compatible = "socionext,uniphier-ld20-peri-clock";
258				#clock-cells = <1>;
259			};
260
261			peri_rst: reset {
262				compatible = "socionext,uniphier-ld20-peri-reset";
263				#reset-cells = <1>;
264			};
265		};
266
267		sd: sdhc@5a400000 {
268			compatible = "socionext,uniphier-sdhc";
269			status = "disabled";
270			reg = <0x5a400000 0x800>;
271			interrupts = <0 76 4>;
272			pinctrl-names = "default";
273			pinctrl-0 = <&pinctrl_sd>;
274			clocks = <&mio_clk 0>;
275			reset-names = "host";
276			resets = <&mio_rst 0>;
277			bus-width = <4>;
278		};
279
280		soc-glue@5f800000 {
281			compatible = "socionext,uniphier-soc-glue",
282				     "simple-mfd", "syscon";
283			reg = <0x5f800000 0x2000>;
284			u-boot,dm-pre-reloc;
285
286			pinctrl: pinctrl {
287				compatible = "socionext,uniphier-ld20-pinctrl";
288				u-boot,dm-pre-reloc;
289			};
290		};
291
292		aidet@5fc20000 {
293			compatible = "simple-mfd", "syscon";
294			reg = <0x5fc20000 0x200>;
295		};
296
297		gic: interrupt-controller@5fe00000 {
298			compatible = "arm,gic-v3";
299			reg = <0x5fe00000 0x10000>,	/* GICD */
300			      <0x5fe80000 0x80000>;	/* GICR */
301			interrupt-controller;
302			#interrupt-cells = <3>;
303			interrupts = <1 9 4>;
304		};
305
306		sysctrl@61840000 {
307			compatible = "socionext,uniphier-sysctrl",
308				     "simple-mfd", "syscon";
309			reg = <0x61840000 0x4000>;
310
311			sys_clk: clock {
312				compatible = "socionext,uniphier-ld20-clock";
313				#clock-cells = <1>;
314			};
315
316			sys_rst: reset {
317				compatible = "socionext,uniphier-ld20-reset";
318				#reset-cells = <1>;
319			};
320		};
321	};
322};
323
324/include/ "uniphier-pinctrl.dtsi"
325