1/* 2 * Device Tree Source for UniPhier LD20 SoC 3 * 4 * Copyright (C) 2015-2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 */ 9 10/memreserve/ 0x80000000 0x02000000; 11 12/ { 13 compatible = "socionext,uniphier-ld20"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&gic>; 17 18 cpus { 19 #address-cells = <2>; 20 #size-cells = <0>; 21 22 cpu-map { 23 cluster0 { 24 core0 { 25 cpu = <&cpu0>; 26 }; 27 core1 { 28 cpu = <&cpu1>; 29 }; 30 }; 31 32 cluster1 { 33 core0 { 34 cpu = <&cpu2>; 35 }; 36 core1 { 37 cpu = <&cpu3>; 38 }; 39 }; 40 }; 41 42 cpu0: cpu@0 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a72", "arm,armv8"; 45 reg = <0 0x000>; 46 clocks = <&sys_clk 32>; 47 enable-method = "psci"; 48 operating-points-v2 = <&cluster0_opp>; 49 }; 50 51 cpu1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a72", "arm,armv8"; 54 reg = <0 0x001>; 55 clocks = <&sys_clk 32>; 56 enable-method = "psci"; 57 operating-points-v2 = <&cluster0_opp>; 58 }; 59 60 cpu2: cpu@100 { 61 device_type = "cpu"; 62 compatible = "arm,cortex-a53", "arm,armv8"; 63 reg = <0 0x100>; 64 clocks = <&sys_clk 33>; 65 enable-method = "psci"; 66 operating-points-v2 = <&cluster1_opp>; 67 }; 68 69 cpu3: cpu@101 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53", "arm,armv8"; 72 reg = <0 0x101>; 73 clocks = <&sys_clk 33>; 74 enable-method = "psci"; 75 operating-points-v2 = <&cluster1_opp>; 76 }; 77 }; 78 79 cluster0_opp: opp_table0 { 80 compatible = "operating-points-v2"; 81 opp-shared; 82 83 opp-250000000 { 84 opp-hz = /bits/ 64 <250000000>; 85 clock-latency-ns = <300>; 86 }; 87 opp-275000000 { 88 opp-hz = /bits/ 64 <275000000>; 89 clock-latency-ns = <300>; 90 }; 91 opp-500000000 { 92 opp-hz = /bits/ 64 <500000000>; 93 clock-latency-ns = <300>; 94 }; 95 opp-550000000 { 96 opp-hz = /bits/ 64 <550000000>; 97 clock-latency-ns = <300>; 98 }; 99 opp-666667000 { 100 opp-hz = /bits/ 64 <666667000>; 101 clock-latency-ns = <300>; 102 }; 103 opp-733334000 { 104 opp-hz = /bits/ 64 <733334000>; 105 clock-latency-ns = <300>; 106 }; 107 opp-1000000000 { 108 opp-hz = /bits/ 64 <1000000000>; 109 clock-latency-ns = <300>; 110 }; 111 opp-1100000000 { 112 opp-hz = /bits/ 64 <1100000000>; 113 clock-latency-ns = <300>; 114 }; 115 }; 116 117 cluster1_opp: opp_table1 { 118 compatible = "operating-points-v2"; 119 opp-shared; 120 121 opp-250000000 { 122 opp-hz = /bits/ 64 <250000000>; 123 clock-latency-ns = <300>; 124 }; 125 opp-275000000 { 126 opp-hz = /bits/ 64 <275000000>; 127 clock-latency-ns = <300>; 128 }; 129 opp-500000000 { 130 opp-hz = /bits/ 64 <500000000>; 131 clock-latency-ns = <300>; 132 }; 133 opp-550000000 { 134 opp-hz = /bits/ 64 <550000000>; 135 clock-latency-ns = <300>; 136 }; 137 opp-666667000 { 138 opp-hz = /bits/ 64 <666667000>; 139 clock-latency-ns = <300>; 140 }; 141 opp-733334000 { 142 opp-hz = /bits/ 64 <733334000>; 143 clock-latency-ns = <300>; 144 }; 145 opp-1000000000 { 146 opp-hz = /bits/ 64 <1000000000>; 147 clock-latency-ns = <300>; 148 }; 149 opp-1100000000 { 150 opp-hz = /bits/ 64 <1100000000>; 151 clock-latency-ns = <300>; 152 }; 153 }; 154 155 psci { 156 compatible = "arm,psci-1.0"; 157 method = "smc"; 158 }; 159 160 clocks { 161 refclk: ref { 162 compatible = "fixed-clock"; 163 #clock-cells = <0>; 164 clock-frequency = <25000000>; 165 }; 166 }; 167 168 timer { 169 compatible = "arm,armv8-timer"; 170 interrupts = <1 13 4>, 171 <1 14 4>, 172 <1 11 4>, 173 <1 10 4>; 174 }; 175 176 soc@0 { 177 compatible = "simple-bus"; 178 #address-cells = <1>; 179 #size-cells = <1>; 180 ranges = <0 0 0 0xffffffff>; 181 182 serial0: serial@54006800 { 183 compatible = "socionext,uniphier-uart"; 184 status = "disabled"; 185 reg = <0x54006800 0x40>; 186 interrupts = <0 33 4>; 187 pinctrl-names = "default"; 188 pinctrl-0 = <&pinctrl_uart0>; 189 clocks = <&peri_clk 0>; 190 clock-frequency = <58820000>; 191 }; 192 193 serial1: serial@54006900 { 194 compatible = "socionext,uniphier-uart"; 195 status = "disabled"; 196 reg = <0x54006900 0x40>; 197 interrupts = <0 35 4>; 198 pinctrl-names = "default"; 199 pinctrl-0 = <&pinctrl_uart1>; 200 clocks = <&peri_clk 1>; 201 clock-frequency = <58820000>; 202 }; 203 204 serial2: serial@54006a00 { 205 compatible = "socionext,uniphier-uart"; 206 status = "disabled"; 207 reg = <0x54006a00 0x40>; 208 interrupts = <0 37 4>; 209 pinctrl-names = "default"; 210 pinctrl-0 = <&pinctrl_uart2>; 211 clocks = <&peri_clk 2>; 212 clock-frequency = <58820000>; 213 }; 214 215 serial3: serial@54006b00 { 216 compatible = "socionext,uniphier-uart"; 217 status = "disabled"; 218 reg = <0x54006b00 0x40>; 219 interrupts = <0 177 4>; 220 pinctrl-names = "default"; 221 pinctrl-0 = <&pinctrl_uart3>; 222 clocks = <&peri_clk 3>; 223 clock-frequency = <58820000>; 224 }; 225 226 gpio: gpio@55000000 { 227 compatible = "socionext,uniphier-gpio"; 228 reg = <0x55000000 0x200>; 229 interrupt-parent = <&aidet>; 230 interrupt-controller; 231 #interrupt-cells = <2>; 232 gpio-controller; 233 #gpio-cells = <2>; 234 gpio-ranges = <&pinctrl 0 0 0>, 235 <&pinctrl 96 0 0>, 236 <&pinctrl 160 0 0>; 237 gpio-ranges-group-names = "gpio_range0", 238 "gpio_range1", 239 "gpio_range2"; 240 ngpios = <205>; 241 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 242 <21 217 3>; 243 }; 244 245 adamv@57920000 { 246 compatible = "socionext,uniphier-ld20-adamv", 247 "simple-mfd", "syscon"; 248 reg = <0x57920000 0x1000>; 249 250 adamv_rst: reset { 251 compatible = "socionext,uniphier-ld20-adamv-reset"; 252 #reset-cells = <1>; 253 }; 254 }; 255 256 i2c0: i2c@58780000 { 257 compatible = "socionext,uniphier-fi2c"; 258 status = "disabled"; 259 reg = <0x58780000 0x80>; 260 #address-cells = <1>; 261 #size-cells = <0>; 262 interrupts = <0 41 4>; 263 pinctrl-names = "default"; 264 pinctrl-0 = <&pinctrl_i2c0>; 265 clocks = <&peri_clk 4>; 266 clock-frequency = <100000>; 267 }; 268 269 i2c1: i2c@58781000 { 270 compatible = "socionext,uniphier-fi2c"; 271 status = "disabled"; 272 reg = <0x58781000 0x80>; 273 #address-cells = <1>; 274 #size-cells = <0>; 275 interrupts = <0 42 4>; 276 pinctrl-names = "default"; 277 pinctrl-0 = <&pinctrl_i2c1>; 278 clocks = <&peri_clk 5>; 279 clock-frequency = <100000>; 280 }; 281 282 i2c2: i2c@58782000 { 283 compatible = "socionext,uniphier-fi2c"; 284 reg = <0x58782000 0x80>; 285 #address-cells = <1>; 286 #size-cells = <0>; 287 interrupts = <0 43 4>; 288 clocks = <&peri_clk 6>; 289 clock-frequency = <400000>; 290 }; 291 292 i2c3: i2c@58783000 { 293 compatible = "socionext,uniphier-fi2c"; 294 status = "disabled"; 295 reg = <0x58783000 0x80>; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 interrupts = <0 44 4>; 299 pinctrl-names = "default"; 300 pinctrl-0 = <&pinctrl_i2c3>; 301 clocks = <&peri_clk 7>; 302 clock-frequency = <100000>; 303 }; 304 305 i2c4: i2c@58784000 { 306 compatible = "socionext,uniphier-fi2c"; 307 status = "disabled"; 308 reg = <0x58784000 0x80>; 309 #address-cells = <1>; 310 #size-cells = <0>; 311 interrupts = <0 45 4>; 312 pinctrl-names = "default"; 313 pinctrl-0 = <&pinctrl_i2c4>; 314 clocks = <&peri_clk 8>; 315 clock-frequency = <100000>; 316 }; 317 318 i2c5: i2c@58785000 { 319 compatible = "socionext,uniphier-fi2c"; 320 reg = <0x58785000 0x80>; 321 #address-cells = <1>; 322 #size-cells = <0>; 323 interrupts = <0 25 4>; 324 clocks = <&peri_clk 9>; 325 clock-frequency = <400000>; 326 }; 327 328 system_bus: system-bus@58c00000 { 329 compatible = "socionext,uniphier-system-bus"; 330 status = "disabled"; 331 reg = <0x58c00000 0x400>; 332 #address-cells = <2>; 333 #size-cells = <1>; 334 pinctrl-names = "default"; 335 pinctrl-0 = <&pinctrl_system_bus>; 336 }; 337 338 smpctrl@59801000 { 339 compatible = "socionext,uniphier-smpctrl"; 340 reg = <0x59801000 0x400>; 341 }; 342 343 sdctrl@59810000 { 344 compatible = "socionext,uniphier-ld20-sdctrl", 345 "simple-mfd", "syscon"; 346 reg = <0x59810000 0x400>; 347 348 sd_clk: clock { 349 compatible = "socionext,uniphier-ld20-sd-clock"; 350 #clock-cells = <1>; 351 }; 352 353 sd_rst: reset { 354 compatible = "socionext,uniphier-ld20-sd-reset"; 355 #reset-cells = <1>; 356 }; 357 }; 358 359 perictrl@59820000 { 360 compatible = "socionext,uniphier-ld20-perictrl", 361 "simple-mfd", "syscon"; 362 reg = <0x59820000 0x200>; 363 364 peri_clk: clock { 365 compatible = "socionext,uniphier-ld20-peri-clock"; 366 #clock-cells = <1>; 367 }; 368 369 peri_rst: reset { 370 compatible = "socionext,uniphier-ld20-peri-reset"; 371 #reset-cells = <1>; 372 }; 373 }; 374 375 emmc: sdhc@5a000000 { 376 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 377 reg = <0x5a000000 0x400>; 378 interrupts = <0 78 4>; 379 pinctrl-names = "default"; 380 pinctrl-0 = <&pinctrl_emmc_1v8>; 381 clocks = <&sys_clk 4>; 382 bus-width = <8>; 383 mmc-ddr-1_8v; 384 mmc-hs200-1_8v; 385 cdns,phy-input-delay-legacy = <4>; 386 cdns,phy-input-delay-mmc-highspeed = <2>; 387 cdns,phy-input-delay-mmc-ddr = <3>; 388 cdns,phy-dll-delay-sdclk = <21>; 389 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 390 }; 391 392 sd: sdhc@5a400000 { 393 compatible = "socionext,uniphier-sdhc"; 394 status = "disabled"; 395 reg = <0x5a400000 0x800>; 396 interrupts = <0 76 4>; 397 pinctrl-names = "default"; 398 pinctrl-0 = <&pinctrl_sd>; 399 clocks = <&sd_clk 0>; 400 reset-names = "host"; 401 resets = <&sd_rst 0>; 402 bus-width = <4>; 403 cap-sd-highspeed; 404 }; 405 406 soc-glue@5f800000 { 407 compatible = "socionext,uniphier-ld20-soc-glue", 408 "simple-mfd", "syscon"; 409 reg = <0x5f800000 0x2000>; 410 411 pinctrl: pinctrl { 412 compatible = "socionext,uniphier-ld20-pinctrl"; 413 }; 414 }; 415 416 aidet: aidet@5fc20000 { 417 compatible = "socionext,uniphier-ld20-aidet"; 418 reg = <0x5fc20000 0x200>; 419 interrupt-controller; 420 #interrupt-cells = <2>; 421 }; 422 423 gic: interrupt-controller@5fe00000 { 424 compatible = "arm,gic-v3"; 425 reg = <0x5fe00000 0x10000>, /* GICD */ 426 <0x5fe80000 0x80000>; /* GICR */ 427 interrupt-controller; 428 #interrupt-cells = <3>; 429 interrupts = <1 9 4>; 430 }; 431 432 sysctrl@61840000 { 433 compatible = "socionext,uniphier-ld20-sysctrl", 434 "simple-mfd", "syscon"; 435 reg = <0x61840000 0x10000>; 436 437 sys_clk: clock { 438 compatible = "socionext,uniphier-ld20-clock"; 439 #clock-cells = <1>; 440 }; 441 442 sys_rst: reset { 443 compatible = "socionext,uniphier-ld20-reset"; 444 #reset-cells = <1>; 445 }; 446 447 watchdog { 448 compatible = "socionext,uniphier-wdt"; 449 }; 450 }; 451 452 usb: usb@65b00000 { 453 compatible = "socionext,uniphier-ld20-dwc3"; 454 reg = <0x65b00000 0x1000>; 455 #address-cells = <1>; 456 #size-cells = <1>; 457 ranges; 458 pinctrl-names = "default"; 459 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>, 460 <&pinctrl_usb2>, <&pinctrl_usb3>; 461 dwc3@65a00000 { 462 compatible = "snps,dwc3"; 463 reg = <0x65a00000 0x10000>; 464 interrupts = <0 134 4>; 465 dr_mode = "host"; 466 tx-fifo-resize; 467 }; 468 }; 469 470 nand: nand@68000000 { 471 compatible = "socionext,uniphier-denali-nand-v5b"; 472 status = "disabled"; 473 reg-names = "nand_data", "denali_reg"; 474 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 475 interrupts = <0 65 4>; 476 pinctrl-names = "default"; 477 pinctrl-0 = <&pinctrl_nand>; 478 clocks = <&sys_clk 2>; 479 }; 480 }; 481}; 482 483#include "uniphier-pinctrl.dtsi" 484