152159d27SMasahiro Yamada/* 252159d27SMasahiro Yamada * Device Tree Source for UniPhier LD20 SoC 352159d27SMasahiro Yamada * 452159d27SMasahiro Yamada * Copyright (C) 2015-2016 Socionext Inc. 552159d27SMasahiro Yamada * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 652159d27SMasahiro Yamada * 752159d27SMasahiro Yamada * SPDX-License-Identifier: GPL-2.0+ X11 852159d27SMasahiro Yamada */ 952159d27SMasahiro Yamada 10*cd62214dSMasahiro Yamada/memreserve/ 0x80000000 0x00080000; 1152159d27SMasahiro Yamada 1252159d27SMasahiro Yamada/ { 1352159d27SMasahiro Yamada compatible = "socionext,uniphier-ld20"; 1452159d27SMasahiro Yamada #address-cells = <2>; 1552159d27SMasahiro Yamada #size-cells = <2>; 1652159d27SMasahiro Yamada interrupt-parent = <&gic>; 1752159d27SMasahiro Yamada 1852159d27SMasahiro Yamada cpus { 1952159d27SMasahiro Yamada #address-cells = <2>; 2052159d27SMasahiro Yamada #size-cells = <0>; 2152159d27SMasahiro Yamada 2252159d27SMasahiro Yamada cpu-map { 2352159d27SMasahiro Yamada cluster0 { 2452159d27SMasahiro Yamada core0 { 2552159d27SMasahiro Yamada cpu = <&cpu0>; 2652159d27SMasahiro Yamada }; 2752159d27SMasahiro Yamada core1 { 2852159d27SMasahiro Yamada cpu = <&cpu1>; 2952159d27SMasahiro Yamada }; 3052159d27SMasahiro Yamada }; 3152159d27SMasahiro Yamada 3252159d27SMasahiro Yamada cluster1 { 3352159d27SMasahiro Yamada core0 { 3452159d27SMasahiro Yamada cpu = <&cpu2>; 3552159d27SMasahiro Yamada }; 3652159d27SMasahiro Yamada core1 { 3752159d27SMasahiro Yamada cpu = <&cpu3>; 3852159d27SMasahiro Yamada }; 3952159d27SMasahiro Yamada }; 4052159d27SMasahiro Yamada }; 4152159d27SMasahiro Yamada 4252159d27SMasahiro Yamada cpu0: cpu@0 { 4352159d27SMasahiro Yamada device_type = "cpu"; 4452159d27SMasahiro Yamada compatible = "arm,cortex-a72", "arm,armv8"; 4552159d27SMasahiro Yamada reg = <0 0x000>; 46*cd62214dSMasahiro Yamada clocks = <&sys_clk 32>; 47*cd62214dSMasahiro Yamada enable-method = "psci"; 48*cd62214dSMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 4952159d27SMasahiro Yamada }; 5052159d27SMasahiro Yamada 5152159d27SMasahiro Yamada cpu1: cpu@1 { 5252159d27SMasahiro Yamada device_type = "cpu"; 5352159d27SMasahiro Yamada compatible = "arm,cortex-a72", "arm,armv8"; 5452159d27SMasahiro Yamada reg = <0 0x001>; 55*cd62214dSMasahiro Yamada clocks = <&sys_clk 32>; 56*cd62214dSMasahiro Yamada enable-method = "psci"; 57*cd62214dSMasahiro Yamada operating-points-v2 = <&cluster0_opp>; 5852159d27SMasahiro Yamada }; 5952159d27SMasahiro Yamada 6052159d27SMasahiro Yamada cpu2: cpu@100 { 6152159d27SMasahiro Yamada device_type = "cpu"; 6252159d27SMasahiro Yamada compatible = "arm,cortex-a53", "arm,armv8"; 6352159d27SMasahiro Yamada reg = <0 0x100>; 64*cd62214dSMasahiro Yamada clocks = <&sys_clk 33>; 65*cd62214dSMasahiro Yamada enable-method = "psci"; 66*cd62214dSMasahiro Yamada operating-points-v2 = <&cluster1_opp>; 6752159d27SMasahiro Yamada }; 6852159d27SMasahiro Yamada 6952159d27SMasahiro Yamada cpu3: cpu@101 { 7052159d27SMasahiro Yamada device_type = "cpu"; 7152159d27SMasahiro Yamada compatible = "arm,cortex-a53", "arm,armv8"; 7252159d27SMasahiro Yamada reg = <0 0x101>; 73*cd62214dSMasahiro Yamada clocks = <&sys_clk 33>; 74*cd62214dSMasahiro Yamada enable-method = "psci"; 75*cd62214dSMasahiro Yamada operating-points-v2 = <&cluster1_opp>; 7652159d27SMasahiro Yamada }; 7752159d27SMasahiro Yamada }; 7852159d27SMasahiro Yamada 79*cd62214dSMasahiro Yamada cluster0_opp: opp_table0 { 80*cd62214dSMasahiro Yamada compatible = "operating-points-v2"; 81*cd62214dSMasahiro Yamada opp-shared; 82*cd62214dSMasahiro Yamada 83*cd62214dSMasahiro Yamada opp@250000000 { 84*cd62214dSMasahiro Yamada opp-hz = /bits/ 64 <250000000>; 85*cd62214dSMasahiro Yamada clock-latency-ns = <300>; 86*cd62214dSMasahiro Yamada }; 87*cd62214dSMasahiro Yamada opp@275000000 { 88*cd62214dSMasahiro Yamada opp-hz = /bits/ 64 <275000000>; 89*cd62214dSMasahiro Yamada clock-latency-ns = <300>; 90*cd62214dSMasahiro Yamada }; 91*cd62214dSMasahiro Yamada opp@500000000 { 92*cd62214dSMasahiro Yamada opp-hz = /bits/ 64 <500000000>; 93*cd62214dSMasahiro Yamada clock-latency-ns = <300>; 94*cd62214dSMasahiro Yamada }; 95*cd62214dSMasahiro Yamada opp@550000000 { 96*cd62214dSMasahiro Yamada opp-hz = /bits/ 64 <550000000>; 97*cd62214dSMasahiro Yamada clock-latency-ns = <300>; 98*cd62214dSMasahiro Yamada }; 99*cd62214dSMasahiro Yamada opp@666667000 { 100*cd62214dSMasahiro Yamada opp-hz = /bits/ 64 <666667000>; 101*cd62214dSMasahiro Yamada clock-latency-ns = <300>; 102*cd62214dSMasahiro Yamada }; 103*cd62214dSMasahiro Yamada opp@733334000 { 104*cd62214dSMasahiro Yamada opp-hz = /bits/ 64 <733334000>; 105*cd62214dSMasahiro Yamada clock-latency-ns = <300>; 106*cd62214dSMasahiro Yamada }; 107*cd62214dSMasahiro Yamada opp@1000000000 { 108*cd62214dSMasahiro Yamada opp-hz = /bits/ 64 <1000000000>; 109*cd62214dSMasahiro Yamada clock-latency-ns = <300>; 110*cd62214dSMasahiro Yamada }; 111*cd62214dSMasahiro Yamada opp@1100000000 { 112*cd62214dSMasahiro Yamada opp-hz = /bits/ 64 <1100000000>; 113*cd62214dSMasahiro Yamada clock-latency-ns = <300>; 114*cd62214dSMasahiro Yamada }; 115*cd62214dSMasahiro Yamada }; 116*cd62214dSMasahiro Yamada 117*cd62214dSMasahiro Yamada cluster1_opp: opp_table1 { 118*cd62214dSMasahiro Yamada compatible = "operating-points-v2"; 119*cd62214dSMasahiro Yamada opp-shared; 120*cd62214dSMasahiro Yamada 121*cd62214dSMasahiro Yamada opp@250000000 { 122*cd62214dSMasahiro Yamada opp-hz = /bits/ 64 <250000000>; 123*cd62214dSMasahiro Yamada clock-latency-ns = <300>; 124*cd62214dSMasahiro Yamada }; 125*cd62214dSMasahiro Yamada opp@275000000 { 126*cd62214dSMasahiro Yamada opp-hz = /bits/ 64 <275000000>; 127*cd62214dSMasahiro Yamada clock-latency-ns = <300>; 128*cd62214dSMasahiro Yamada }; 129*cd62214dSMasahiro Yamada opp@500000000 { 130*cd62214dSMasahiro Yamada opp-hz = /bits/ 64 <500000000>; 131*cd62214dSMasahiro Yamada clock-latency-ns = <300>; 132*cd62214dSMasahiro Yamada }; 133*cd62214dSMasahiro Yamada opp@550000000 { 134*cd62214dSMasahiro Yamada opp-hz = /bits/ 64 <550000000>; 135*cd62214dSMasahiro Yamada clock-latency-ns = <300>; 136*cd62214dSMasahiro Yamada }; 137*cd62214dSMasahiro Yamada opp@666667000 { 138*cd62214dSMasahiro Yamada opp-hz = /bits/ 64 <666667000>; 139*cd62214dSMasahiro Yamada clock-latency-ns = <300>; 140*cd62214dSMasahiro Yamada }; 141*cd62214dSMasahiro Yamada opp@733334000 { 142*cd62214dSMasahiro Yamada opp-hz = /bits/ 64 <733334000>; 143*cd62214dSMasahiro Yamada clock-latency-ns = <300>; 144*cd62214dSMasahiro Yamada }; 145*cd62214dSMasahiro Yamada opp@1000000000 { 146*cd62214dSMasahiro Yamada opp-hz = /bits/ 64 <1000000000>; 147*cd62214dSMasahiro Yamada clock-latency-ns = <300>; 148*cd62214dSMasahiro Yamada }; 149*cd62214dSMasahiro Yamada opp@1100000000 { 150*cd62214dSMasahiro Yamada opp-hz = /bits/ 64 <1100000000>; 151*cd62214dSMasahiro Yamada clock-latency-ns = <300>; 152*cd62214dSMasahiro Yamada }; 153*cd62214dSMasahiro Yamada }; 154*cd62214dSMasahiro Yamada 155*cd62214dSMasahiro Yamada psci { 156*cd62214dSMasahiro Yamada compatible = "arm,psci-1.0"; 157*cd62214dSMasahiro Yamada method = "smc"; 158*cd62214dSMasahiro Yamada }; 159*cd62214dSMasahiro Yamada 16052159d27SMasahiro Yamada clocks { 16152159d27SMasahiro Yamada refclk: ref { 16252159d27SMasahiro Yamada compatible = "fixed-clock"; 16352159d27SMasahiro Yamada #clock-cells = <0>; 16452159d27SMasahiro Yamada clock-frequency = <25000000>; 16552159d27SMasahiro Yamada }; 16652159d27SMasahiro Yamada }; 16752159d27SMasahiro Yamada 16852159d27SMasahiro Yamada timer { 16952159d27SMasahiro Yamada compatible = "arm,armv8-timer"; 17052159d27SMasahiro Yamada interrupts = <1 13 4>, 17152159d27SMasahiro Yamada <1 14 4>, 17252159d27SMasahiro Yamada <1 11 4>, 17352159d27SMasahiro Yamada <1 10 4>; 17452159d27SMasahiro Yamada }; 17552159d27SMasahiro Yamada 17652159d27SMasahiro Yamada soc { 17752159d27SMasahiro Yamada compatible = "simple-bus"; 17852159d27SMasahiro Yamada #address-cells = <1>; 17952159d27SMasahiro Yamada #size-cells = <1>; 18052159d27SMasahiro Yamada ranges = <0 0 0 0xffffffff>; 18152159d27SMasahiro Yamada u-boot,dm-pre-reloc; 18252159d27SMasahiro Yamada 18352159d27SMasahiro Yamada serial0: serial@54006800 { 18452159d27SMasahiro Yamada compatible = "socionext,uniphier-uart"; 18552159d27SMasahiro Yamada status = "disabled"; 18652159d27SMasahiro Yamada reg = <0x54006800 0x40>; 18752159d27SMasahiro Yamada interrupts = <0 33 4>; 18852159d27SMasahiro Yamada pinctrl-names = "default"; 18952159d27SMasahiro Yamada pinctrl-0 = <&pinctrl_uart0>; 19052159d27SMasahiro Yamada clocks = <&peri_clk 0>; 19152159d27SMasahiro Yamada clock-frequency = <58820000>; 19252159d27SMasahiro Yamada }; 19352159d27SMasahiro Yamada 19452159d27SMasahiro Yamada serial1: serial@54006900 { 19552159d27SMasahiro Yamada compatible = "socionext,uniphier-uart"; 19652159d27SMasahiro Yamada status = "disabled"; 19752159d27SMasahiro Yamada reg = <0x54006900 0x40>; 19852159d27SMasahiro Yamada interrupts = <0 35 4>; 19952159d27SMasahiro Yamada pinctrl-names = "default"; 20052159d27SMasahiro Yamada pinctrl-0 = <&pinctrl_uart1>; 20152159d27SMasahiro Yamada clocks = <&peri_clk 1>; 20252159d27SMasahiro Yamada clock-frequency = <58820000>; 20352159d27SMasahiro Yamada }; 20452159d27SMasahiro Yamada 20552159d27SMasahiro Yamada serial2: serial@54006a00 { 20652159d27SMasahiro Yamada compatible = "socionext,uniphier-uart"; 20752159d27SMasahiro Yamada status = "disabled"; 20852159d27SMasahiro Yamada reg = <0x54006a00 0x40>; 20952159d27SMasahiro Yamada interrupts = <0 37 4>; 21052159d27SMasahiro Yamada pinctrl-names = "default"; 21152159d27SMasahiro Yamada pinctrl-0 = <&pinctrl_uart2>; 21252159d27SMasahiro Yamada clocks = <&peri_clk 2>; 21352159d27SMasahiro Yamada clock-frequency = <58820000>; 21452159d27SMasahiro Yamada }; 21552159d27SMasahiro Yamada 21652159d27SMasahiro Yamada serial3: serial@54006b00 { 21752159d27SMasahiro Yamada compatible = "socionext,uniphier-uart"; 21852159d27SMasahiro Yamada status = "disabled"; 21952159d27SMasahiro Yamada reg = <0x54006b00 0x40>; 22052159d27SMasahiro Yamada interrupts = <0 177 4>; 22152159d27SMasahiro Yamada pinctrl-names = "default"; 22252159d27SMasahiro Yamada pinctrl-0 = <&pinctrl_uart3>; 22352159d27SMasahiro Yamada clocks = <&peri_clk 3>; 22452159d27SMasahiro Yamada clock-frequency = <58820000>; 22552159d27SMasahiro Yamada }; 22652159d27SMasahiro Yamada 22752159d27SMasahiro Yamada i2c0: i2c@58780000 { 22852159d27SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 22952159d27SMasahiro Yamada status = "disabled"; 23052159d27SMasahiro Yamada reg = <0x58780000 0x80>; 23152159d27SMasahiro Yamada #address-cells = <1>; 23252159d27SMasahiro Yamada #size-cells = <0>; 23352159d27SMasahiro Yamada interrupts = <0 41 4>; 23452159d27SMasahiro Yamada pinctrl-names = "default"; 23552159d27SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c0>; 236*cd62214dSMasahiro Yamada clocks = <&peri_clk 4>; 23752159d27SMasahiro Yamada clock-frequency = <100000>; 23852159d27SMasahiro Yamada }; 23952159d27SMasahiro Yamada 24052159d27SMasahiro Yamada i2c1: i2c@58781000 { 24152159d27SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 24252159d27SMasahiro Yamada status = "disabled"; 24352159d27SMasahiro Yamada reg = <0x58781000 0x80>; 24452159d27SMasahiro Yamada #address-cells = <1>; 24552159d27SMasahiro Yamada #size-cells = <0>; 24652159d27SMasahiro Yamada interrupts = <0 42 4>; 24752159d27SMasahiro Yamada pinctrl-names = "default"; 24852159d27SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c1>; 249*cd62214dSMasahiro Yamada clocks = <&peri_clk 5>; 25052159d27SMasahiro Yamada clock-frequency = <100000>; 25152159d27SMasahiro Yamada }; 25252159d27SMasahiro Yamada 25352159d27SMasahiro Yamada i2c2: i2c@58782000 { 25452159d27SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 25552159d27SMasahiro Yamada reg = <0x58782000 0x80>; 25652159d27SMasahiro Yamada #address-cells = <1>; 25752159d27SMasahiro Yamada #size-cells = <0>; 25852159d27SMasahiro Yamada interrupts = <0 43 4>; 259*cd62214dSMasahiro Yamada clocks = <&peri_clk 6>; 26052159d27SMasahiro Yamada clock-frequency = <400000>; 26152159d27SMasahiro Yamada }; 26252159d27SMasahiro Yamada 26352159d27SMasahiro Yamada i2c3: i2c@58783000 { 26452159d27SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 26552159d27SMasahiro Yamada status = "disabled"; 26652159d27SMasahiro Yamada reg = <0x58783000 0x80>; 26752159d27SMasahiro Yamada #address-cells = <1>; 26852159d27SMasahiro Yamada #size-cells = <0>; 26952159d27SMasahiro Yamada interrupts = <0 44 4>; 27052159d27SMasahiro Yamada pinctrl-names = "default"; 27152159d27SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c3>; 272*cd62214dSMasahiro Yamada clocks = <&peri_clk 7>; 27352159d27SMasahiro Yamada clock-frequency = <100000>; 27452159d27SMasahiro Yamada }; 27552159d27SMasahiro Yamada 27652159d27SMasahiro Yamada i2c4: i2c@58784000 { 27752159d27SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 27852159d27SMasahiro Yamada status = "disabled"; 27952159d27SMasahiro Yamada reg = <0x58784000 0x80>; 28052159d27SMasahiro Yamada #address-cells = <1>; 28152159d27SMasahiro Yamada #size-cells = <0>; 28252159d27SMasahiro Yamada interrupts = <0 45 4>; 28352159d27SMasahiro Yamada pinctrl-names = "default"; 28452159d27SMasahiro Yamada pinctrl-0 = <&pinctrl_i2c4>; 285*cd62214dSMasahiro Yamada clocks = <&peri_clk 8>; 28652159d27SMasahiro Yamada clock-frequency = <100000>; 28752159d27SMasahiro Yamada }; 28852159d27SMasahiro Yamada 28952159d27SMasahiro Yamada i2c5: i2c@58785000 { 29052159d27SMasahiro Yamada compatible = "socionext,uniphier-fi2c"; 29152159d27SMasahiro Yamada reg = <0x58785000 0x80>; 29252159d27SMasahiro Yamada #address-cells = <1>; 29352159d27SMasahiro Yamada #size-cells = <0>; 29452159d27SMasahiro Yamada interrupts = <0 25 4>; 295*cd62214dSMasahiro Yamada clocks = <&peri_clk 9>; 29652159d27SMasahiro Yamada clock-frequency = <400000>; 29752159d27SMasahiro Yamada }; 29852159d27SMasahiro Yamada 29952159d27SMasahiro Yamada system_bus: system-bus@58c00000 { 30052159d27SMasahiro Yamada compatible = "socionext,uniphier-system-bus"; 30152159d27SMasahiro Yamada status = "disabled"; 30252159d27SMasahiro Yamada reg = <0x58c00000 0x400>; 30352159d27SMasahiro Yamada #address-cells = <2>; 30452159d27SMasahiro Yamada #size-cells = <1>; 30552159d27SMasahiro Yamada pinctrl-names = "default"; 30652159d27SMasahiro Yamada pinctrl-0 = <&pinctrl_system_bus>; 30752159d27SMasahiro Yamada }; 30852159d27SMasahiro Yamada 30952159d27SMasahiro Yamada smpctrl@59800000 { 31052159d27SMasahiro Yamada compatible = "socionext,uniphier-smpctrl"; 31152159d27SMasahiro Yamada reg = <0x59801000 0x400>; 31252159d27SMasahiro Yamada }; 31352159d27SMasahiro Yamada 314*cd62214dSMasahiro Yamada sdctrl@59810000 { 315*cd62214dSMasahiro Yamada compatible = "socionext,uniphier-ld20-sdctrl", 31652159d27SMasahiro Yamada "simple-mfd", "syscon"; 31752159d27SMasahiro Yamada reg = <0x59810000 0x800>; 31852159d27SMasahiro Yamada 319*cd62214dSMasahiro Yamada sd_clk: clock { 320*cd62214dSMasahiro Yamada compatible = "socionext,uniphier-ld20-sd-clock"; 32152159d27SMasahiro Yamada #clock-cells = <1>; 32252159d27SMasahiro Yamada }; 32352159d27SMasahiro Yamada 324*cd62214dSMasahiro Yamada sd_rst: reset { 325*cd62214dSMasahiro Yamada compatible = "socionext,uniphier-ld20-sd-reset"; 32652159d27SMasahiro Yamada #reset-cells = <1>; 32752159d27SMasahiro Yamada }; 32852159d27SMasahiro Yamada }; 32952159d27SMasahiro Yamada 33052159d27SMasahiro Yamada perictrl@59820000 { 331*cd62214dSMasahiro Yamada compatible = "socionext,uniphier-ld20-perictrl", 33252159d27SMasahiro Yamada "simple-mfd", "syscon"; 33352159d27SMasahiro Yamada reg = <0x59820000 0x200>; 33452159d27SMasahiro Yamada 33552159d27SMasahiro Yamada peri_clk: clock { 33652159d27SMasahiro Yamada compatible = "socionext,uniphier-ld20-peri-clock"; 33752159d27SMasahiro Yamada #clock-cells = <1>; 33852159d27SMasahiro Yamada }; 33952159d27SMasahiro Yamada 34052159d27SMasahiro Yamada peri_rst: reset { 34152159d27SMasahiro Yamada compatible = "socionext,uniphier-ld20-peri-reset"; 34252159d27SMasahiro Yamada #reset-cells = <1>; 34352159d27SMasahiro Yamada }; 34452159d27SMasahiro Yamada }; 34552159d27SMasahiro Yamada 346*cd62214dSMasahiro Yamada emmc: sdhc@5a000000 { 347*cd62214dSMasahiro Yamada compatible = "cdns,sd4hc"; 348*cd62214dSMasahiro Yamada reg = <0x5a000000 0x400>; 349*cd62214dSMasahiro Yamada interrupts = <0 78 4>; 350*cd62214dSMasahiro Yamada pinctrl-names = "default"; 351*cd62214dSMasahiro Yamada pinctrl-0 = <&pinctrl_emmc_1v8>; 352*cd62214dSMasahiro Yamada clocks = <&sys_clk 4>; 353*cd62214dSMasahiro Yamada bus-width = <8>; 354*cd62214dSMasahiro Yamada mmc-ddr-1_8v; 355*cd62214dSMasahiro Yamada mmc-hs200-1_8v; 356*cd62214dSMasahiro Yamada /* mmc-hs400-1_8v; support depends on board design */ 357*cd62214dSMasahiro Yamada }; 358*cd62214dSMasahiro Yamada 35952159d27SMasahiro Yamada sd: sdhc@5a400000 { 36052159d27SMasahiro Yamada compatible = "socionext,uniphier-sdhc"; 36152159d27SMasahiro Yamada status = "disabled"; 36252159d27SMasahiro Yamada reg = <0x5a400000 0x800>; 36352159d27SMasahiro Yamada interrupts = <0 76 4>; 36452159d27SMasahiro Yamada pinctrl-names = "default"; 36552159d27SMasahiro Yamada pinctrl-0 = <&pinctrl_sd>; 366*cd62214dSMasahiro Yamada clocks = <&sd_clk 0>; 36752159d27SMasahiro Yamada reset-names = "host"; 368*cd62214dSMasahiro Yamada resets = <&sd_rst 0>; 36952159d27SMasahiro Yamada bus-width = <4>; 370*cd62214dSMasahiro Yamada cap-sd-highspeed; 37152159d27SMasahiro Yamada }; 37252159d27SMasahiro Yamada 37352159d27SMasahiro Yamada soc-glue@5f800000 { 374*cd62214dSMasahiro Yamada compatible = "socionext,uniphier-ld20-soc-glue", 37552159d27SMasahiro Yamada "simple-mfd", "syscon"; 37652159d27SMasahiro Yamada reg = <0x5f800000 0x2000>; 37752159d27SMasahiro Yamada u-boot,dm-pre-reloc; 37852159d27SMasahiro Yamada 37952159d27SMasahiro Yamada pinctrl: pinctrl { 38052159d27SMasahiro Yamada compatible = "socionext,uniphier-ld20-pinctrl"; 38152159d27SMasahiro Yamada u-boot,dm-pre-reloc; 38252159d27SMasahiro Yamada }; 38352159d27SMasahiro Yamada }; 38452159d27SMasahiro Yamada 38552159d27SMasahiro Yamada aidet@5fc20000 { 38652159d27SMasahiro Yamada compatible = "simple-mfd", "syscon"; 38752159d27SMasahiro Yamada reg = <0x5fc20000 0x200>; 38852159d27SMasahiro Yamada }; 38952159d27SMasahiro Yamada 39052159d27SMasahiro Yamada gic: interrupt-controller@5fe00000 { 39152159d27SMasahiro Yamada compatible = "arm,gic-v3"; 39252159d27SMasahiro Yamada reg = <0x5fe00000 0x10000>, /* GICD */ 39352159d27SMasahiro Yamada <0x5fe80000 0x80000>; /* GICR */ 39452159d27SMasahiro Yamada interrupt-controller; 39552159d27SMasahiro Yamada #interrupt-cells = <3>; 39652159d27SMasahiro Yamada interrupts = <1 9 4>; 39752159d27SMasahiro Yamada }; 39852159d27SMasahiro Yamada 39952159d27SMasahiro Yamada sysctrl@61840000 { 400*cd62214dSMasahiro Yamada compatible = "socionext,uniphier-ld20-sysctrl", 40152159d27SMasahiro Yamada "simple-mfd", "syscon"; 402*cd62214dSMasahiro Yamada reg = <0x61840000 0x10000>; 40352159d27SMasahiro Yamada 40452159d27SMasahiro Yamada sys_clk: clock { 40552159d27SMasahiro Yamada compatible = "socionext,uniphier-ld20-clock"; 40652159d27SMasahiro Yamada #clock-cells = <1>; 40752159d27SMasahiro Yamada }; 40852159d27SMasahiro Yamada 40952159d27SMasahiro Yamada sys_rst: reset { 41052159d27SMasahiro Yamada compatible = "socionext,uniphier-ld20-reset"; 41152159d27SMasahiro Yamada #reset-cells = <1>; 41252159d27SMasahiro Yamada }; 41352159d27SMasahiro Yamada }; 414*cd62214dSMasahiro Yamada 415*cd62214dSMasahiro Yamada usb: usb@65b00000 { 416*cd62214dSMasahiro Yamada compatible = "socionext,uniphier-ld20-dwc3"; 417*cd62214dSMasahiro Yamada reg = <0x65b00000 0x1000>; 418*cd62214dSMasahiro Yamada #address-cells = <1>; 419*cd62214dSMasahiro Yamada #size-cells = <1>; 420*cd62214dSMasahiro Yamada ranges; 421*cd62214dSMasahiro Yamada pinctrl-names = "default"; 422*cd62214dSMasahiro Yamada pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>, 423*cd62214dSMasahiro Yamada <&pinctrl_usb2>, <&pinctrl_usb3>; 424*cd62214dSMasahiro Yamada dwc3@65a00000 { 425*cd62214dSMasahiro Yamada compatible = "snps,dwc3"; 426*cd62214dSMasahiro Yamada reg = <0x65a00000 0x10000>; 427*cd62214dSMasahiro Yamada interrupts = <0 134 4>; 428*cd62214dSMasahiro Yamada tx-fifo-resize; 429*cd62214dSMasahiro Yamada }; 430*cd62214dSMasahiro Yamada }; 431*cd62214dSMasahiro Yamada 432*cd62214dSMasahiro Yamada nand: nand@68000000 { 433*cd62214dSMasahiro Yamada compatible = "socionext,denali-nand-v5b"; 434*cd62214dSMasahiro Yamada status = "disabled"; 435*cd62214dSMasahiro Yamada reg-names = "nand_data", "denali_reg"; 436*cd62214dSMasahiro Yamada reg = <0x68000000 0x20>, <0x68100000 0x1000>; 437*cd62214dSMasahiro Yamada interrupts = <0 65 4>; 438*cd62214dSMasahiro Yamada pinctrl-names = "default"; 439*cd62214dSMasahiro Yamada pinctrl-0 = <&pinctrl_nand>; 440*cd62214dSMasahiro Yamada clocks = <&sys_clk 2>; 441*cd62214dSMasahiro Yamada nand-ecc-strength = <8>; 442*cd62214dSMasahiro Yamada }; 44352159d27SMasahiro Yamada }; 44452159d27SMasahiro Yamada}; 44552159d27SMasahiro Yamada 44652159d27SMasahiro Yamada/include/ "uniphier-pinctrl.dtsi" 447