1/* 2 * Device Tree Source for UniPhier LD11 SoC 3 * 4 * Copyright (C) 2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 */ 9 10/memreserve/ 0x80000000 0x02000000; 11 12/ { 13 compatible = "socionext,uniphier-ld11"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&gic>; 17 18 cpus { 19 #address-cells = <2>; 20 #size-cells = <0>; 21 22 cpu-map { 23 cluster0 { 24 core0 { 25 cpu = <&cpu0>; 26 }; 27 core1 { 28 cpu = <&cpu1>; 29 }; 30 }; 31 }; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53", "arm,armv8"; 36 reg = <0 0x000>; 37 clocks = <&sys_clk 33>; 38 enable-method = "psci"; 39 operating-points-v2 = <&cluster0_opp>; 40 }; 41 42 cpu1: cpu@1 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a53", "arm,armv8"; 45 reg = <0 0x001>; 46 clocks = <&sys_clk 33>; 47 enable-method = "psci"; 48 operating-points-v2 = <&cluster0_opp>; 49 }; 50 }; 51 52 cluster0_opp: opp_table { 53 compatible = "operating-points-v2"; 54 opp-shared; 55 56 opp-245000000 { 57 opp-hz = /bits/ 64 <245000000>; 58 clock-latency-ns = <300>; 59 }; 60 opp-250000000 { 61 opp-hz = /bits/ 64 <250000000>; 62 clock-latency-ns = <300>; 63 }; 64 opp-490000000 { 65 opp-hz = /bits/ 64 <490000000>; 66 clock-latency-ns = <300>; 67 }; 68 opp-500000000 { 69 opp-hz = /bits/ 64 <500000000>; 70 clock-latency-ns = <300>; 71 }; 72 opp-653334000 { 73 opp-hz = /bits/ 64 <653334000>; 74 clock-latency-ns = <300>; 75 }; 76 opp-666667000 { 77 opp-hz = /bits/ 64 <666667000>; 78 clock-latency-ns = <300>; 79 }; 80 opp-980000000 { 81 opp-hz = /bits/ 64 <980000000>; 82 clock-latency-ns = <300>; 83 }; 84 }; 85 86 psci { 87 compatible = "arm,psci-1.0"; 88 method = "smc"; 89 }; 90 91 clocks { 92 refclk: ref { 93 compatible = "fixed-clock"; 94 #clock-cells = <0>; 95 clock-frequency = <25000000>; 96 }; 97 }; 98 99 timer { 100 compatible = "arm,armv8-timer"; 101 interrupts = <1 13 4>, 102 <1 14 4>, 103 <1 11 4>, 104 <1 10 4>; 105 }; 106 107 soc@0 { 108 compatible = "simple-bus"; 109 #address-cells = <1>; 110 #size-cells = <1>; 111 ranges = <0 0 0 0xffffffff>; 112 113 serial0: serial@54006800 { 114 compatible = "socionext,uniphier-uart"; 115 status = "disabled"; 116 reg = <0x54006800 0x40>; 117 interrupts = <0 33 4>; 118 pinctrl-names = "default"; 119 pinctrl-0 = <&pinctrl_uart0>; 120 clocks = <&peri_clk 0>; 121 clock-frequency = <58820000>; 122 }; 123 124 serial1: serial@54006900 { 125 compatible = "socionext,uniphier-uart"; 126 status = "disabled"; 127 reg = <0x54006900 0x40>; 128 interrupts = <0 35 4>; 129 pinctrl-names = "default"; 130 pinctrl-0 = <&pinctrl_uart1>; 131 clocks = <&peri_clk 1>; 132 clock-frequency = <58820000>; 133 }; 134 135 serial2: serial@54006a00 { 136 compatible = "socionext,uniphier-uart"; 137 status = "disabled"; 138 reg = <0x54006a00 0x40>; 139 interrupts = <0 37 4>; 140 pinctrl-names = "default"; 141 pinctrl-0 = <&pinctrl_uart2>; 142 clocks = <&peri_clk 2>; 143 clock-frequency = <58820000>; 144 }; 145 146 serial3: serial@54006b00 { 147 compatible = "socionext,uniphier-uart"; 148 status = "disabled"; 149 reg = <0x54006b00 0x40>; 150 interrupts = <0 177 4>; 151 pinctrl-names = "default"; 152 pinctrl-0 = <&pinctrl_uart3>; 153 clocks = <&peri_clk 3>; 154 clock-frequency = <58820000>; 155 }; 156 157 i2c0: i2c@58780000 { 158 compatible = "socionext,uniphier-fi2c"; 159 status = "disabled"; 160 reg = <0x58780000 0x80>; 161 #address-cells = <1>; 162 #size-cells = <0>; 163 interrupts = <0 41 4>; 164 pinctrl-names = "default"; 165 pinctrl-0 = <&pinctrl_i2c0>; 166 clocks = <&peri_clk 4>; 167 clock-frequency = <100000>; 168 }; 169 170 i2c1: i2c@58781000 { 171 compatible = "socionext,uniphier-fi2c"; 172 status = "disabled"; 173 reg = <0x58781000 0x80>; 174 #address-cells = <1>; 175 #size-cells = <0>; 176 interrupts = <0 42 4>; 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_i2c1>; 179 clocks = <&peri_clk 5>; 180 clock-frequency = <100000>; 181 }; 182 183 i2c2: i2c@58782000 { 184 compatible = "socionext,uniphier-fi2c"; 185 reg = <0x58782000 0x80>; 186 #address-cells = <1>; 187 #size-cells = <0>; 188 interrupts = <0 43 4>; 189 clocks = <&peri_clk 6>; 190 clock-frequency = <400000>; 191 }; 192 193 i2c3: i2c@58783000 { 194 compatible = "socionext,uniphier-fi2c"; 195 status = "disabled"; 196 reg = <0x58783000 0x80>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 interrupts = <0 44 4>; 200 pinctrl-names = "default"; 201 pinctrl-0 = <&pinctrl_i2c3>; 202 clocks = <&peri_clk 7>; 203 clock-frequency = <100000>; 204 }; 205 206 i2c4: i2c@58784000 { 207 compatible = "socionext,uniphier-fi2c"; 208 status = "disabled"; 209 reg = <0x58784000 0x80>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 interrupts = <0 45 4>; 213 pinctrl-names = "default"; 214 pinctrl-0 = <&pinctrl_i2c4>; 215 clocks = <&peri_clk 8>; 216 clock-frequency = <100000>; 217 }; 218 219 i2c5: i2c@58785000 { 220 compatible = "socionext,uniphier-fi2c"; 221 reg = <0x58785000 0x80>; 222 #address-cells = <1>; 223 #size-cells = <0>; 224 interrupts = <0 25 4>; 225 clocks = <&peri_clk 9>; 226 clock-frequency = <400000>; 227 }; 228 229 system_bus: system-bus@58c00000 { 230 compatible = "socionext,uniphier-system-bus"; 231 status = "disabled"; 232 reg = <0x58c00000 0x400>; 233 #address-cells = <2>; 234 #size-cells = <1>; 235 pinctrl-names = "default"; 236 pinctrl-0 = <&pinctrl_system_bus>; 237 }; 238 239 smpctrl@59801000 { 240 compatible = "socionext,uniphier-smpctrl"; 241 reg = <0x59801000 0x400>; 242 }; 243 244 sdctrl@59810000 { 245 compatible = "socionext,uniphier-ld11-sdctrl", 246 "simple-mfd", "syscon"; 247 reg = <0x59810000 0x400>; 248 249 sd_rst: reset { 250 compatible = "socionext,uniphier-ld11-sd-reset"; 251 #reset-cells = <1>; 252 }; 253 }; 254 255 perictrl@59820000 { 256 compatible = "socionext,uniphier-ld11-perictrl", 257 "simple-mfd", "syscon"; 258 reg = <0x59820000 0x200>; 259 260 peri_clk: clock { 261 compatible = "socionext,uniphier-ld11-peri-clock"; 262 #clock-cells = <1>; 263 }; 264 265 peri_rst: reset { 266 compatible = "socionext,uniphier-ld11-peri-reset"; 267 #reset-cells = <1>; 268 }; 269 }; 270 271 emmc: sdhc@5a000000 { 272 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 273 reg = <0x5a000000 0x400>; 274 interrupts = <0 78 4>; 275 pinctrl-names = "default"; 276 pinctrl-0 = <&pinctrl_emmc_1v8>; 277 clocks = <&sys_clk 4>; 278 bus-width = <8>; 279 mmc-ddr-1_8v; 280 mmc-hs200-1_8v; 281 cdns,phy-input-delay-legacy = <4>; 282 cdns,phy-input-delay-mmc-highspeed = <2>; 283 cdns,phy-input-delay-mmc-ddr = <3>; 284 cdns,phy-dll-delay-sdclk = <21>; 285 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 286 }; 287 288 usb0: usb@5a800100 { 289 compatible = "socionext,uniphier-ehci", "generic-ehci"; 290 status = "disabled"; 291 reg = <0x5a800100 0x100>; 292 interrupts = <0 243 4>; 293 pinctrl-names = "default"; 294 pinctrl-0 = <&pinctrl_usb0>; 295 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; 296 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 297 <&mio_rst 12>; 298 }; 299 300 usb1: usb@5a810100 { 301 compatible = "socionext,uniphier-ehci", "generic-ehci"; 302 status = "disabled"; 303 reg = <0x5a810100 0x100>; 304 interrupts = <0 244 4>; 305 pinctrl-names = "default"; 306 pinctrl-0 = <&pinctrl_usb1>; 307 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; 308 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 309 <&mio_rst 13>; 310 }; 311 312 usb2: usb@5a820100 { 313 compatible = "socionext,uniphier-ehci", "generic-ehci"; 314 status = "disabled"; 315 reg = <0x5a820100 0x100>; 316 interrupts = <0 245 4>; 317 pinctrl-names = "default"; 318 pinctrl-0 = <&pinctrl_usb2>; 319 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; 320 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, 321 <&mio_rst 14>; 322 }; 323 324 mioctrl@5b3e0000 { 325 compatible = "socionext,uniphier-ld11-mioctrl", 326 "simple-mfd", "syscon"; 327 reg = <0x5b3e0000 0x800>; 328 329 mio_clk: clock { 330 compatible = "socionext,uniphier-ld11-mio-clock"; 331 #clock-cells = <1>; 332 }; 333 334 mio_rst: reset { 335 compatible = "socionext,uniphier-ld11-mio-reset"; 336 #reset-cells = <1>; 337 resets = <&sys_rst 7>; 338 }; 339 }; 340 341 soc-glue@5f800000 { 342 compatible = "socionext,uniphier-ld11-soc-glue", 343 "simple-mfd", "syscon"; 344 reg = <0x5f800000 0x2000>; 345 346 pinctrl: pinctrl { 347 compatible = "socionext,uniphier-ld11-pinctrl"; 348 }; 349 }; 350 351 aidet: aidet@5fc20000 { 352 compatible = "socionext,uniphier-ld11-aidet"; 353 reg = <0x5fc20000 0x200>; 354 interrupt-controller; 355 #interrupt-cells = <2>; 356 }; 357 358 gic: interrupt-controller@5fe00000 { 359 compatible = "arm,gic-v3"; 360 reg = <0x5fe00000 0x10000>, /* GICD */ 361 <0x5fe40000 0x80000>; /* GICR */ 362 interrupt-controller; 363 #interrupt-cells = <3>; 364 interrupts = <1 9 4>; 365 }; 366 367 sysctrl@61840000 { 368 compatible = "socionext,uniphier-ld11-sysctrl", 369 "simple-mfd", "syscon"; 370 reg = <0x61840000 0x10000>; 371 372 sys_clk: clock { 373 compatible = "socionext,uniphier-ld11-clock"; 374 #clock-cells = <1>; 375 }; 376 377 sys_rst: reset { 378 compatible = "socionext,uniphier-ld11-reset"; 379 #reset-cells = <1>; 380 }; 381 382 watchdog { 383 compatible = "socionext,uniphier-wdt"; 384 }; 385 }; 386 387 nand: nand@68000000 { 388 compatible = "socionext,uniphier-denali-nand-v5b"; 389 status = "disabled"; 390 reg-names = "nand_data", "denali_reg"; 391 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 392 interrupts = <0 65 4>; 393 pinctrl-names = "default"; 394 pinctrl-0 = <&pinctrl_nand>; 395 clocks = <&sys_clk 2>; 396 }; 397 }; 398}; 399 400#include "uniphier-pinctrl.dtsi" 401