1/* 2 * Device Tree Source for UniPhier LD11 SoC 3 * 4 * Copyright (C) 2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 */ 9 10/memreserve/ 0x80000000 0x02000000; 11 12/ { 13 compatible = "socionext,uniphier-ld11"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&gic>; 17 18 cpus { 19 #address-cells = <2>; 20 #size-cells = <0>; 21 22 cpu-map { 23 cluster0 { 24 core0 { 25 cpu = <&cpu0>; 26 }; 27 core1 { 28 cpu = <&cpu1>; 29 }; 30 }; 31 }; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53", "arm,armv8"; 36 reg = <0 0x000>; 37 clocks = <&sys_clk 33>; 38 enable-method = "psci"; 39 operating-points-v2 = <&cluster0_opp>; 40 }; 41 42 cpu1: cpu@1 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a53", "arm,armv8"; 45 reg = <0 0x001>; 46 clocks = <&sys_clk 33>; 47 enable-method = "psci"; 48 operating-points-v2 = <&cluster0_opp>; 49 }; 50 }; 51 52 cluster0_opp: opp_table { 53 compatible = "operating-points-v2"; 54 opp-shared; 55 56 opp-245000000 { 57 opp-hz = /bits/ 64 <245000000>; 58 clock-latency-ns = <300>; 59 }; 60 opp-250000000 { 61 opp-hz = /bits/ 64 <250000000>; 62 clock-latency-ns = <300>; 63 }; 64 opp-490000000 { 65 opp-hz = /bits/ 64 <490000000>; 66 clock-latency-ns = <300>; 67 }; 68 opp-500000000 { 69 opp-hz = /bits/ 64 <500000000>; 70 clock-latency-ns = <300>; 71 }; 72 opp-653334000 { 73 opp-hz = /bits/ 64 <653334000>; 74 clock-latency-ns = <300>; 75 }; 76 opp-666667000 { 77 opp-hz = /bits/ 64 <666667000>; 78 clock-latency-ns = <300>; 79 }; 80 opp-980000000 { 81 opp-hz = /bits/ 64 <980000000>; 82 clock-latency-ns = <300>; 83 }; 84 }; 85 86 psci { 87 compatible = "arm,psci-1.0"; 88 method = "smc"; 89 }; 90 91 clocks { 92 refclk: ref { 93 compatible = "fixed-clock"; 94 #clock-cells = <0>; 95 clock-frequency = <25000000>; 96 }; 97 }; 98 99 timer { 100 compatible = "arm,armv8-timer"; 101 interrupts = <1 13 4>, 102 <1 14 4>, 103 <1 11 4>, 104 <1 10 4>; 105 }; 106 107 soc@0 { 108 compatible = "simple-bus"; 109 #address-cells = <1>; 110 #size-cells = <1>; 111 ranges = <0 0 0 0xffffffff>; 112 113 serial0: serial@54006800 { 114 compatible = "socionext,uniphier-uart"; 115 status = "disabled"; 116 reg = <0x54006800 0x40>; 117 interrupts = <0 33 4>; 118 pinctrl-names = "default"; 119 pinctrl-0 = <&pinctrl_uart0>; 120 clocks = <&peri_clk 0>; 121 clock-frequency = <58820000>; 122 }; 123 124 serial1: serial@54006900 { 125 compatible = "socionext,uniphier-uart"; 126 status = "disabled"; 127 reg = <0x54006900 0x40>; 128 interrupts = <0 35 4>; 129 pinctrl-names = "default"; 130 pinctrl-0 = <&pinctrl_uart1>; 131 clocks = <&peri_clk 1>; 132 clock-frequency = <58820000>; 133 }; 134 135 serial2: serial@54006a00 { 136 compatible = "socionext,uniphier-uart"; 137 status = "disabled"; 138 reg = <0x54006a00 0x40>; 139 interrupts = <0 37 4>; 140 pinctrl-names = "default"; 141 pinctrl-0 = <&pinctrl_uart2>; 142 clocks = <&peri_clk 2>; 143 clock-frequency = <58820000>; 144 }; 145 146 serial3: serial@54006b00 { 147 compatible = "socionext,uniphier-uart"; 148 status = "disabled"; 149 reg = <0x54006b00 0x40>; 150 interrupts = <0 177 4>; 151 pinctrl-names = "default"; 152 pinctrl-0 = <&pinctrl_uart3>; 153 clocks = <&peri_clk 3>; 154 clock-frequency = <58820000>; 155 }; 156 157 gpio: gpio@55000000 { 158 compatible = "socionext,uniphier-gpio"; 159 reg = <0x55000000 0x200>; 160 interrupt-parent = <&aidet>; 161 interrupt-controller; 162 #interrupt-cells = <2>; 163 gpio-controller; 164 #gpio-cells = <2>; 165 gpio-ranges = <&pinctrl 0 0 0>, 166 <&pinctrl 43 0 0>, 167 <&pinctrl 51 0 0>, 168 <&pinctrl 96 0 0>, 169 <&pinctrl 160 0 0>, 170 <&pinctrl 184 0 0>; 171 gpio-ranges-group-names = "gpio_range0", 172 "gpio_range1", 173 "gpio_range2", 174 "gpio_range3", 175 "gpio_range4", 176 "gpio_range5"; 177 ngpios = <200>; 178 }; 179 180 i2c0: i2c@58780000 { 181 compatible = "socionext,uniphier-fi2c"; 182 status = "disabled"; 183 reg = <0x58780000 0x80>; 184 #address-cells = <1>; 185 #size-cells = <0>; 186 interrupts = <0 41 4>; 187 pinctrl-names = "default"; 188 pinctrl-0 = <&pinctrl_i2c0>; 189 clocks = <&peri_clk 4>; 190 clock-frequency = <100000>; 191 }; 192 193 i2c1: i2c@58781000 { 194 compatible = "socionext,uniphier-fi2c"; 195 status = "disabled"; 196 reg = <0x58781000 0x80>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 interrupts = <0 42 4>; 200 pinctrl-names = "default"; 201 pinctrl-0 = <&pinctrl_i2c1>; 202 clocks = <&peri_clk 5>; 203 clock-frequency = <100000>; 204 }; 205 206 i2c2: i2c@58782000 { 207 compatible = "socionext,uniphier-fi2c"; 208 reg = <0x58782000 0x80>; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 interrupts = <0 43 4>; 212 clocks = <&peri_clk 6>; 213 clock-frequency = <400000>; 214 }; 215 216 i2c3: i2c@58783000 { 217 compatible = "socionext,uniphier-fi2c"; 218 status = "disabled"; 219 reg = <0x58783000 0x80>; 220 #address-cells = <1>; 221 #size-cells = <0>; 222 interrupts = <0 44 4>; 223 pinctrl-names = "default"; 224 pinctrl-0 = <&pinctrl_i2c3>; 225 clocks = <&peri_clk 7>; 226 clock-frequency = <100000>; 227 }; 228 229 i2c4: i2c@58784000 { 230 compatible = "socionext,uniphier-fi2c"; 231 status = "disabled"; 232 reg = <0x58784000 0x80>; 233 #address-cells = <1>; 234 #size-cells = <0>; 235 interrupts = <0 45 4>; 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_i2c4>; 238 clocks = <&peri_clk 8>; 239 clock-frequency = <100000>; 240 }; 241 242 i2c5: i2c@58785000 { 243 compatible = "socionext,uniphier-fi2c"; 244 reg = <0x58785000 0x80>; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 interrupts = <0 25 4>; 248 clocks = <&peri_clk 9>; 249 clock-frequency = <400000>; 250 }; 251 252 system_bus: system-bus@58c00000 { 253 compatible = "socionext,uniphier-system-bus"; 254 status = "disabled"; 255 reg = <0x58c00000 0x400>; 256 #address-cells = <2>; 257 #size-cells = <1>; 258 pinctrl-names = "default"; 259 pinctrl-0 = <&pinctrl_system_bus>; 260 }; 261 262 smpctrl@59801000 { 263 compatible = "socionext,uniphier-smpctrl"; 264 reg = <0x59801000 0x400>; 265 }; 266 267 sdctrl@59810000 { 268 compatible = "socionext,uniphier-ld11-sdctrl", 269 "simple-mfd", "syscon"; 270 reg = <0x59810000 0x400>; 271 272 sd_rst: reset { 273 compatible = "socionext,uniphier-ld11-sd-reset"; 274 #reset-cells = <1>; 275 }; 276 }; 277 278 perictrl@59820000 { 279 compatible = "socionext,uniphier-ld11-perictrl", 280 "simple-mfd", "syscon"; 281 reg = <0x59820000 0x200>; 282 283 peri_clk: clock { 284 compatible = "socionext,uniphier-ld11-peri-clock"; 285 #clock-cells = <1>; 286 }; 287 288 peri_rst: reset { 289 compatible = "socionext,uniphier-ld11-peri-reset"; 290 #reset-cells = <1>; 291 }; 292 }; 293 294 emmc: sdhc@5a000000 { 295 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 296 reg = <0x5a000000 0x400>; 297 interrupts = <0 78 4>; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&pinctrl_emmc_1v8>; 300 clocks = <&sys_clk 4>; 301 bus-width = <8>; 302 mmc-ddr-1_8v; 303 mmc-hs200-1_8v; 304 cdns,phy-input-delay-legacy = <4>; 305 cdns,phy-input-delay-mmc-highspeed = <2>; 306 cdns,phy-input-delay-mmc-ddr = <3>; 307 cdns,phy-dll-delay-sdclk = <21>; 308 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 309 }; 310 311 usb0: usb@5a800100 { 312 compatible = "socionext,uniphier-ehci", "generic-ehci"; 313 status = "disabled"; 314 reg = <0x5a800100 0x100>; 315 interrupts = <0 243 4>; 316 pinctrl-names = "default"; 317 pinctrl-0 = <&pinctrl_usb0>; 318 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; 319 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 320 <&mio_rst 12>; 321 }; 322 323 usb1: usb@5a810100 { 324 compatible = "socionext,uniphier-ehci", "generic-ehci"; 325 status = "disabled"; 326 reg = <0x5a810100 0x100>; 327 interrupts = <0 244 4>; 328 pinctrl-names = "default"; 329 pinctrl-0 = <&pinctrl_usb1>; 330 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; 331 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 332 <&mio_rst 13>; 333 }; 334 335 usb2: usb@5a820100 { 336 compatible = "socionext,uniphier-ehci", "generic-ehci"; 337 status = "disabled"; 338 reg = <0x5a820100 0x100>; 339 interrupts = <0 245 4>; 340 pinctrl-names = "default"; 341 pinctrl-0 = <&pinctrl_usb2>; 342 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; 343 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, 344 <&mio_rst 14>; 345 }; 346 347 mioctrl@5b3e0000 { 348 compatible = "socionext,uniphier-ld11-mioctrl", 349 "simple-mfd", "syscon"; 350 reg = <0x5b3e0000 0x800>; 351 352 mio_clk: clock { 353 compatible = "socionext,uniphier-ld11-mio-clock"; 354 #clock-cells = <1>; 355 }; 356 357 mio_rst: reset { 358 compatible = "socionext,uniphier-ld11-mio-reset"; 359 #reset-cells = <1>; 360 resets = <&sys_rst 7>; 361 }; 362 }; 363 364 soc-glue@5f800000 { 365 compatible = "socionext,uniphier-ld11-soc-glue", 366 "simple-mfd", "syscon"; 367 reg = <0x5f800000 0x2000>; 368 369 pinctrl: pinctrl { 370 compatible = "socionext,uniphier-ld11-pinctrl"; 371 }; 372 }; 373 374 aidet: aidet@5fc20000 { 375 compatible = "socionext,uniphier-ld11-aidet"; 376 reg = <0x5fc20000 0x200>; 377 interrupt-controller; 378 #interrupt-cells = <2>; 379 }; 380 381 gic: interrupt-controller@5fe00000 { 382 compatible = "arm,gic-v3"; 383 reg = <0x5fe00000 0x10000>, /* GICD */ 384 <0x5fe40000 0x80000>; /* GICR */ 385 interrupt-controller; 386 #interrupt-cells = <3>; 387 interrupts = <1 9 4>; 388 }; 389 390 sysctrl@61840000 { 391 compatible = "socionext,uniphier-ld11-sysctrl", 392 "simple-mfd", "syscon"; 393 reg = <0x61840000 0x10000>; 394 395 sys_clk: clock { 396 compatible = "socionext,uniphier-ld11-clock"; 397 #clock-cells = <1>; 398 }; 399 400 sys_rst: reset { 401 compatible = "socionext,uniphier-ld11-reset"; 402 #reset-cells = <1>; 403 }; 404 405 watchdog { 406 compatible = "socionext,uniphier-wdt"; 407 }; 408 }; 409 410 nand: nand@68000000 { 411 compatible = "socionext,uniphier-denali-nand-v5b"; 412 status = "disabled"; 413 reg-names = "nand_data", "denali_reg"; 414 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 415 interrupts = <0 65 4>; 416 pinctrl-names = "default"; 417 pinctrl-0 = <&pinctrl_nand>; 418 clocks = <&sys_clk 2>; 419 }; 420 }; 421}; 422 423#include "uniphier-pinctrl.dtsi" 424