1/* 2 * Device Tree Source for UniPhier LD11 SoC 3 * 4 * Copyright (C) 2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * This file is dual-licensed: you can use it either under the terms 8 * of the GPL or the X11 license, at your option. Note that this dual 9 * licensing only applies to this file, and not this project as a 10 * whole. 11 * 12 * a) This file is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of the 15 * License, or (at your option) any later version. 16 * 17 * This file is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * Or, alternatively, 23 * 24 * b) Permission is hereby granted, free of charge, to any person 25 * obtaining a copy of this software and associated documentation 26 * files (the "Software"), to deal in the Software without 27 * restriction, including without limitation the rights to use, 28 * copy, modify, merge, publish, distribute, sublicense, and/or 29 * sell copies of the Software, and to permit persons to whom the 30 * Software is furnished to do so, subject to the following 31 * conditions: 32 * 33 * The above copyright notice and this permission notice shall be 34 * included in all copies or substantial portions of the Software. 35 * 36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 43 * OTHER DEALINGS IN THE SOFTWARE. 44 */ 45 46/memreserve/ 0x80000000 0x00080000; 47 48/ { 49 compatible = "socionext,uniphier-ld11"; 50 #address-cells = <2>; 51 #size-cells = <2>; 52 interrupt-parent = <&gic>; 53 54 cpus { 55 #address-cells = <2>; 56 #size-cells = <0>; 57 58 cpu-map { 59 cluster0 { 60 core0 { 61 cpu = <&cpu0>; 62 }; 63 core1 { 64 cpu = <&cpu1>; 65 }; 66 }; 67 }; 68 69 cpu0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53", "arm,armv8"; 72 reg = <0 0x000>; 73 clocks = <&sys_clk 33>; 74 enable-method = "psci"; 75 operating-points-v2 = <&cluster0_opp>; 76 }; 77 78 cpu1: cpu@1 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53", "arm,armv8"; 81 reg = <0 0x001>; 82 clocks = <&sys_clk 33>; 83 enable-method = "psci"; 84 operating-points-v2 = <&cluster0_opp>; 85 }; 86 }; 87 88 cluster0_opp: opp_table { 89 compatible = "operating-points-v2"; 90 opp-shared; 91 92 opp-245000000 { 93 opp-hz = /bits/ 64 <245000000>; 94 clock-latency-ns = <300>; 95 }; 96 opp-250000000 { 97 opp-hz = /bits/ 64 <250000000>; 98 clock-latency-ns = <300>; 99 }; 100 opp-490000000 { 101 opp-hz = /bits/ 64 <490000000>; 102 clock-latency-ns = <300>; 103 }; 104 opp-500000000 { 105 opp-hz = /bits/ 64 <500000000>; 106 clock-latency-ns = <300>; 107 }; 108 opp-653334000 { 109 opp-hz = /bits/ 64 <653334000>; 110 clock-latency-ns = <300>; 111 }; 112 opp-666667000 { 113 opp-hz = /bits/ 64 <666667000>; 114 clock-latency-ns = <300>; 115 }; 116 opp-980000000 { 117 opp-hz = /bits/ 64 <980000000>; 118 clock-latency-ns = <300>; 119 }; 120 }; 121 122 psci { 123 compatible = "arm,psci-1.0"; 124 method = "smc"; 125 }; 126 127 clocks { 128 refclk: ref { 129 compatible = "fixed-clock"; 130 #clock-cells = <0>; 131 clock-frequency = <25000000>; 132 }; 133 }; 134 135 timer { 136 compatible = "arm,armv8-timer"; 137 interrupts = <1 13 4>, 138 <1 14 4>, 139 <1 11 4>, 140 <1 10 4>; 141 }; 142 143 soc@0 { 144 compatible = "simple-bus"; 145 #address-cells = <1>; 146 #size-cells = <1>; 147 ranges = <0 0 0 0xffffffff>; 148 u-boot,dm-pre-reloc; 149 150 serial0: serial@54006800 { 151 compatible = "socionext,uniphier-uart"; 152 status = "disabled"; 153 reg = <0x54006800 0x40>; 154 interrupts = <0 33 4>; 155 pinctrl-names = "default"; 156 pinctrl-0 = <&pinctrl_uart0>; 157 clocks = <&peri_clk 0>; 158 clock-frequency = <58820000>; 159 }; 160 161 serial1: serial@54006900 { 162 compatible = "socionext,uniphier-uart"; 163 status = "disabled"; 164 reg = <0x54006900 0x40>; 165 interrupts = <0 35 4>; 166 pinctrl-names = "default"; 167 pinctrl-0 = <&pinctrl_uart1>; 168 clocks = <&peri_clk 1>; 169 clock-frequency = <58820000>; 170 }; 171 172 serial2: serial@54006a00 { 173 compatible = "socionext,uniphier-uart"; 174 status = "disabled"; 175 reg = <0x54006a00 0x40>; 176 interrupts = <0 37 4>; 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_uart2>; 179 clocks = <&peri_clk 2>; 180 clock-frequency = <58820000>; 181 }; 182 183 serial3: serial@54006b00 { 184 compatible = "socionext,uniphier-uart"; 185 status = "disabled"; 186 reg = <0x54006b00 0x40>; 187 interrupts = <0 177 4>; 188 pinctrl-names = "default"; 189 pinctrl-0 = <&pinctrl_uart3>; 190 clocks = <&peri_clk 3>; 191 clock-frequency = <58820000>; 192 }; 193 194 i2c0: i2c@58780000 { 195 compatible = "socionext,uniphier-fi2c"; 196 status = "disabled"; 197 reg = <0x58780000 0x80>; 198 #address-cells = <1>; 199 #size-cells = <0>; 200 interrupts = <0 41 4>; 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinctrl_i2c0>; 203 clocks = <&peri_clk 4>; 204 clock-frequency = <100000>; 205 }; 206 207 i2c1: i2c@58781000 { 208 compatible = "socionext,uniphier-fi2c"; 209 status = "disabled"; 210 reg = <0x58781000 0x80>; 211 #address-cells = <1>; 212 #size-cells = <0>; 213 interrupts = <0 42 4>; 214 pinctrl-names = "default"; 215 pinctrl-0 = <&pinctrl_i2c1>; 216 clocks = <&peri_clk 5>; 217 clock-frequency = <100000>; 218 }; 219 220 i2c2: i2c@58782000 { 221 compatible = "socionext,uniphier-fi2c"; 222 reg = <0x58782000 0x80>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 interrupts = <0 43 4>; 226 clocks = <&peri_clk 6>; 227 clock-frequency = <400000>; 228 }; 229 230 i2c3: i2c@58783000 { 231 compatible = "socionext,uniphier-fi2c"; 232 status = "disabled"; 233 reg = <0x58783000 0x80>; 234 #address-cells = <1>; 235 #size-cells = <0>; 236 interrupts = <0 44 4>; 237 pinctrl-names = "default"; 238 pinctrl-0 = <&pinctrl_i2c3>; 239 clocks = <&peri_clk 7>; 240 clock-frequency = <100000>; 241 }; 242 243 i2c4: i2c@58784000 { 244 compatible = "socionext,uniphier-fi2c"; 245 status = "disabled"; 246 reg = <0x58784000 0x80>; 247 #address-cells = <1>; 248 #size-cells = <0>; 249 interrupts = <0 45 4>; 250 pinctrl-names = "default"; 251 pinctrl-0 = <&pinctrl_i2c4>; 252 clocks = <&peri_clk 8>; 253 clock-frequency = <100000>; 254 }; 255 256 i2c5: i2c@58785000 { 257 compatible = "socionext,uniphier-fi2c"; 258 reg = <0x58785000 0x80>; 259 #address-cells = <1>; 260 #size-cells = <0>; 261 interrupts = <0 25 4>; 262 clocks = <&peri_clk 9>; 263 clock-frequency = <400000>; 264 }; 265 266 system_bus: system-bus@58c00000 { 267 compatible = "socionext,uniphier-system-bus"; 268 status = "disabled"; 269 reg = <0x58c00000 0x400>; 270 #address-cells = <2>; 271 #size-cells = <1>; 272 pinctrl-names = "default"; 273 pinctrl-0 = <&pinctrl_system_bus>; 274 }; 275 276 smpctrl@59801000 { 277 compatible = "socionext,uniphier-smpctrl"; 278 reg = <0x59801000 0x400>; 279 }; 280 281 sdctrl@59810000 { 282 compatible = "socionext,uniphier-ld11-sdctrl", 283 "simple-mfd", "syscon"; 284 reg = <0x59810000 0x400>; 285 286 sd_rst: reset { 287 compatible = "socionext,uniphier-ld11-sd-reset"; 288 #reset-cells = <1>; 289 }; 290 }; 291 292 perictrl@59820000 { 293 compatible = "socionext,uniphier-ld11-perictrl", 294 "simple-mfd", "syscon"; 295 reg = <0x59820000 0x200>; 296 297 peri_clk: clock { 298 compatible = "socionext,uniphier-ld11-peri-clock"; 299 #clock-cells = <1>; 300 }; 301 302 peri_rst: reset { 303 compatible = "socionext,uniphier-ld11-peri-reset"; 304 #reset-cells = <1>; 305 }; 306 }; 307 308 emmc: sdhc@5a000000 { 309 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 310 reg = <0x5a000000 0x400>; 311 interrupts = <0 78 4>; 312 pinctrl-names = "default"; 313 pinctrl-0 = <&pinctrl_emmc_1v8>; 314 clocks = <&sys_clk 4>; 315 bus-width = <8>; 316 mmc-ddr-1_8v; 317 mmc-hs200-1_8v; 318 cdns,phy-input-delay-legacy = <4>; 319 cdns,phy-input-delay-mmc-highspeed = <2>; 320 cdns,phy-input-delay-mmc-ddr = <3>; 321 cdns,phy-dll-delay-sdclk = <21>; 322 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 323 }; 324 325 usb0: usb@5a800100 { 326 compatible = "socionext,uniphier-ehci", "generic-ehci"; 327 status = "disabled"; 328 reg = <0x5a800100 0x100>; 329 interrupts = <0 243 4>; 330 pinctrl-names = "default"; 331 pinctrl-0 = <&pinctrl_usb0>; 332 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; 333 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 334 <&mio_rst 12>; 335 }; 336 337 usb1: usb@5a810100 { 338 compatible = "socionext,uniphier-ehci", "generic-ehci"; 339 status = "disabled"; 340 reg = <0x5a810100 0x100>; 341 interrupts = <0 244 4>; 342 pinctrl-names = "default"; 343 pinctrl-0 = <&pinctrl_usb1>; 344 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; 345 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 346 <&mio_rst 13>; 347 }; 348 349 usb2: usb@5a820100 { 350 compatible = "socionext,uniphier-ehci", "generic-ehci"; 351 status = "disabled"; 352 reg = <0x5a820100 0x100>; 353 interrupts = <0 245 4>; 354 pinctrl-names = "default"; 355 pinctrl-0 = <&pinctrl_usb2>; 356 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; 357 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, 358 <&mio_rst 14>; 359 }; 360 361 mioctrl@5b3e0000 { 362 compatible = "socionext,uniphier-ld11-mioctrl", 363 "simple-mfd", "syscon"; 364 reg = <0x5b3e0000 0x800>; 365 366 mio_clk: clock { 367 compatible = "socionext,uniphier-ld11-mio-clock"; 368 #clock-cells = <1>; 369 }; 370 371 mio_rst: reset { 372 compatible = "socionext,uniphier-ld11-mio-reset"; 373 #reset-cells = <1>; 374 resets = <&sys_rst 7>; 375 }; 376 }; 377 378 soc-glue@5f800000 { 379 compatible = "socionext,uniphier-ld11-soc-glue", 380 "simple-mfd", "syscon"; 381 reg = <0x5f800000 0x2000>; 382 u-boot,dm-pre-reloc; 383 384 pinctrl: pinctrl { 385 compatible = "socionext,uniphier-ld11-pinctrl"; 386 u-boot,dm-pre-reloc; 387 }; 388 }; 389 390 aidet@5fc20000 { 391 compatible = "simple-mfd", "syscon"; 392 reg = <0x5fc20000 0x200>; 393 }; 394 395 gic: interrupt-controller@5fe00000 { 396 compatible = "arm,gic-v3"; 397 reg = <0x5fe00000 0x10000>, /* GICD */ 398 <0x5fe40000 0x80000>; /* GICR */ 399 interrupt-controller; 400 #interrupt-cells = <3>; 401 interrupts = <1 9 4>; 402 }; 403 404 sysctrl@61840000 { 405 compatible = "socionext,uniphier-ld11-sysctrl", 406 "simple-mfd", "syscon"; 407 reg = <0x61840000 0x10000>; 408 409 sys_clk: clock { 410 compatible = "socionext,uniphier-ld11-clock"; 411 #clock-cells = <1>; 412 }; 413 414 sys_rst: reset { 415 compatible = "socionext,uniphier-ld11-reset"; 416 #reset-cells = <1>; 417 }; 418 }; 419 420 nand: nand@68000000 { 421 compatible = "socionext,uniphier-denali-nand-v5b"; 422 status = "disabled"; 423 reg-names = "nand_data", "denali_reg"; 424 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 425 interrupts = <0 65 4>; 426 pinctrl-names = "default"; 427 pinctrl-0 = <&pinctrl_nand>; 428 clocks = <&sys_clk 2>; 429 nand-ecc-strength = <8>; 430 }; 431 }; 432}; 433 434/include/ "uniphier-pinctrl.dtsi" 435