1/* 2 * Device Tree Source for UniPhier LD11 SoC 3 * 4 * Copyright (C) 2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 */ 9 10/memreserve/ 0x80000000 0x02000000; 11 12/ { 13 compatible = "socionext,uniphier-ld11"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&gic>; 17 18 cpus { 19 #address-cells = <2>; 20 #size-cells = <0>; 21 22 cpu-map { 23 cluster0 { 24 core0 { 25 cpu = <&cpu0>; 26 }; 27 core1 { 28 cpu = <&cpu1>; 29 }; 30 }; 31 }; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53", "arm,armv8"; 36 reg = <0 0x000>; 37 clocks = <&sys_clk 33>; 38 enable-method = "psci"; 39 operating-points-v2 = <&cluster0_opp>; 40 }; 41 42 cpu1: cpu@1 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a53", "arm,armv8"; 45 reg = <0 0x001>; 46 clocks = <&sys_clk 33>; 47 enable-method = "psci"; 48 operating-points-v2 = <&cluster0_opp>; 49 }; 50 }; 51 52 cluster0_opp: opp_table { 53 compatible = "operating-points-v2"; 54 opp-shared; 55 56 opp-245000000 { 57 opp-hz = /bits/ 64 <245000000>; 58 clock-latency-ns = <300>; 59 }; 60 opp-250000000 { 61 opp-hz = /bits/ 64 <250000000>; 62 clock-latency-ns = <300>; 63 }; 64 opp-490000000 { 65 opp-hz = /bits/ 64 <490000000>; 66 clock-latency-ns = <300>; 67 }; 68 opp-500000000 { 69 opp-hz = /bits/ 64 <500000000>; 70 clock-latency-ns = <300>; 71 }; 72 opp-653334000 { 73 opp-hz = /bits/ 64 <653334000>; 74 clock-latency-ns = <300>; 75 }; 76 opp-666667000 { 77 opp-hz = /bits/ 64 <666667000>; 78 clock-latency-ns = <300>; 79 }; 80 opp-980000000 { 81 opp-hz = /bits/ 64 <980000000>; 82 clock-latency-ns = <300>; 83 }; 84 }; 85 86 psci { 87 compatible = "arm,psci-1.0"; 88 method = "smc"; 89 }; 90 91 clocks { 92 refclk: ref { 93 compatible = "fixed-clock"; 94 #clock-cells = <0>; 95 clock-frequency = <25000000>; 96 }; 97 }; 98 99 timer { 100 compatible = "arm,armv8-timer"; 101 interrupts = <1 13 4>, 102 <1 14 4>, 103 <1 11 4>, 104 <1 10 4>; 105 }; 106 107 soc@0 { 108 compatible = "simple-bus"; 109 #address-cells = <1>; 110 #size-cells = <1>; 111 ranges = <0 0 0 0xffffffff>; 112 113 serial0: serial@54006800 { 114 compatible = "socionext,uniphier-uart"; 115 status = "disabled"; 116 reg = <0x54006800 0x40>; 117 interrupts = <0 33 4>; 118 pinctrl-names = "default"; 119 pinctrl-0 = <&pinctrl_uart0>; 120 clocks = <&peri_clk 0>; 121 clock-frequency = <58820000>; 122 }; 123 124 serial1: serial@54006900 { 125 compatible = "socionext,uniphier-uart"; 126 status = "disabled"; 127 reg = <0x54006900 0x40>; 128 interrupts = <0 35 4>; 129 pinctrl-names = "default"; 130 pinctrl-0 = <&pinctrl_uart1>; 131 clocks = <&peri_clk 1>; 132 clock-frequency = <58820000>; 133 }; 134 135 serial2: serial@54006a00 { 136 compatible = "socionext,uniphier-uart"; 137 status = "disabled"; 138 reg = <0x54006a00 0x40>; 139 interrupts = <0 37 4>; 140 pinctrl-names = "default"; 141 pinctrl-0 = <&pinctrl_uart2>; 142 clocks = <&peri_clk 2>; 143 clock-frequency = <58820000>; 144 }; 145 146 serial3: serial@54006b00 { 147 compatible = "socionext,uniphier-uart"; 148 status = "disabled"; 149 reg = <0x54006b00 0x40>; 150 interrupts = <0 177 4>; 151 pinctrl-names = "default"; 152 pinctrl-0 = <&pinctrl_uart3>; 153 clocks = <&peri_clk 3>; 154 clock-frequency = <58820000>; 155 }; 156 157 gpio: gpio@55000000 { 158 compatible = "socionext,uniphier-gpio"; 159 reg = <0x55000000 0x200>; 160 interrupt-parent = <&aidet>; 161 interrupt-controller; 162 #interrupt-cells = <2>; 163 gpio-controller; 164 #gpio-cells = <2>; 165 gpio-ranges = <&pinctrl 0 0 0>, 166 <&pinctrl 43 0 0>, 167 <&pinctrl 51 0 0>, 168 <&pinctrl 96 0 0>, 169 <&pinctrl 160 0 0>, 170 <&pinctrl 184 0 0>; 171 gpio-ranges-group-names = "gpio_range0", 172 "gpio_range1", 173 "gpio_range2", 174 "gpio_range3", 175 "gpio_range4", 176 "gpio_range5"; 177 ngpios = <200>; 178 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 179 <21 217 3>; 180 }; 181 182 adamv@57920000 { 183 compatible = "socionext,uniphier-ld11-adamv", 184 "simple-mfd", "syscon"; 185 reg = <0x57920000 0x1000>; 186 187 adamv_rst: reset { 188 compatible = "socionext,uniphier-ld11-adamv-reset"; 189 #reset-cells = <1>; 190 }; 191 }; 192 193 i2c0: i2c@58780000 { 194 compatible = "socionext,uniphier-fi2c"; 195 status = "disabled"; 196 reg = <0x58780000 0x80>; 197 #address-cells = <1>; 198 #size-cells = <0>; 199 interrupts = <0 41 4>; 200 pinctrl-names = "default"; 201 pinctrl-0 = <&pinctrl_i2c0>; 202 clocks = <&peri_clk 4>; 203 clock-frequency = <100000>; 204 }; 205 206 i2c1: i2c@58781000 { 207 compatible = "socionext,uniphier-fi2c"; 208 status = "disabled"; 209 reg = <0x58781000 0x80>; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 interrupts = <0 42 4>; 213 pinctrl-names = "default"; 214 pinctrl-0 = <&pinctrl_i2c1>; 215 clocks = <&peri_clk 5>; 216 clock-frequency = <100000>; 217 }; 218 219 i2c2: i2c@58782000 { 220 compatible = "socionext,uniphier-fi2c"; 221 reg = <0x58782000 0x80>; 222 #address-cells = <1>; 223 #size-cells = <0>; 224 interrupts = <0 43 4>; 225 clocks = <&peri_clk 6>; 226 clock-frequency = <400000>; 227 }; 228 229 i2c3: i2c@58783000 { 230 compatible = "socionext,uniphier-fi2c"; 231 status = "disabled"; 232 reg = <0x58783000 0x80>; 233 #address-cells = <1>; 234 #size-cells = <0>; 235 interrupts = <0 44 4>; 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_i2c3>; 238 clocks = <&peri_clk 7>; 239 clock-frequency = <100000>; 240 }; 241 242 i2c4: i2c@58784000 { 243 compatible = "socionext,uniphier-fi2c"; 244 status = "disabled"; 245 reg = <0x58784000 0x80>; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 interrupts = <0 45 4>; 249 pinctrl-names = "default"; 250 pinctrl-0 = <&pinctrl_i2c4>; 251 clocks = <&peri_clk 8>; 252 clock-frequency = <100000>; 253 }; 254 255 i2c5: i2c@58785000 { 256 compatible = "socionext,uniphier-fi2c"; 257 reg = <0x58785000 0x80>; 258 #address-cells = <1>; 259 #size-cells = <0>; 260 interrupts = <0 25 4>; 261 clocks = <&peri_clk 9>; 262 clock-frequency = <400000>; 263 }; 264 265 system_bus: system-bus@58c00000 { 266 compatible = "socionext,uniphier-system-bus"; 267 status = "disabled"; 268 reg = <0x58c00000 0x400>; 269 #address-cells = <2>; 270 #size-cells = <1>; 271 pinctrl-names = "default"; 272 pinctrl-0 = <&pinctrl_system_bus>; 273 }; 274 275 smpctrl@59801000 { 276 compatible = "socionext,uniphier-smpctrl"; 277 reg = <0x59801000 0x400>; 278 }; 279 280 sdctrl@59810000 { 281 compatible = "socionext,uniphier-ld11-sdctrl", 282 "simple-mfd", "syscon"; 283 reg = <0x59810000 0x400>; 284 285 sd_rst: reset { 286 compatible = "socionext,uniphier-ld11-sd-reset"; 287 #reset-cells = <1>; 288 }; 289 }; 290 291 perictrl@59820000 { 292 compatible = "socionext,uniphier-ld11-perictrl", 293 "simple-mfd", "syscon"; 294 reg = <0x59820000 0x200>; 295 296 peri_clk: clock { 297 compatible = "socionext,uniphier-ld11-peri-clock"; 298 #clock-cells = <1>; 299 }; 300 301 peri_rst: reset { 302 compatible = "socionext,uniphier-ld11-peri-reset"; 303 #reset-cells = <1>; 304 }; 305 }; 306 307 emmc: sdhc@5a000000 { 308 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 309 reg = <0x5a000000 0x400>; 310 interrupts = <0 78 4>; 311 pinctrl-names = "default"; 312 pinctrl-0 = <&pinctrl_emmc_1v8>; 313 clocks = <&sys_clk 4>; 314 bus-width = <8>; 315 mmc-ddr-1_8v; 316 mmc-hs200-1_8v; 317 cdns,phy-input-delay-legacy = <4>; 318 cdns,phy-input-delay-mmc-highspeed = <2>; 319 cdns,phy-input-delay-mmc-ddr = <3>; 320 cdns,phy-dll-delay-sdclk = <21>; 321 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 322 }; 323 324 usb0: usb@5a800100 { 325 compatible = "socionext,uniphier-ehci", "generic-ehci"; 326 status = "disabled"; 327 reg = <0x5a800100 0x100>; 328 interrupts = <0 243 4>; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&pinctrl_usb0>; 331 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; 332 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 333 <&mio_rst 12>; 334 }; 335 336 usb1: usb@5a810100 { 337 compatible = "socionext,uniphier-ehci", "generic-ehci"; 338 status = "disabled"; 339 reg = <0x5a810100 0x100>; 340 interrupts = <0 244 4>; 341 pinctrl-names = "default"; 342 pinctrl-0 = <&pinctrl_usb1>; 343 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; 344 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 345 <&mio_rst 13>; 346 }; 347 348 usb2: usb@5a820100 { 349 compatible = "socionext,uniphier-ehci", "generic-ehci"; 350 status = "disabled"; 351 reg = <0x5a820100 0x100>; 352 interrupts = <0 245 4>; 353 pinctrl-names = "default"; 354 pinctrl-0 = <&pinctrl_usb2>; 355 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; 356 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, 357 <&mio_rst 14>; 358 }; 359 360 mioctrl@5b3e0000 { 361 compatible = "socionext,uniphier-ld11-mioctrl", 362 "simple-mfd", "syscon"; 363 reg = <0x5b3e0000 0x800>; 364 365 mio_clk: clock { 366 compatible = "socionext,uniphier-ld11-mio-clock"; 367 #clock-cells = <1>; 368 }; 369 370 mio_rst: reset { 371 compatible = "socionext,uniphier-ld11-mio-reset"; 372 #reset-cells = <1>; 373 resets = <&sys_rst 7>; 374 }; 375 }; 376 377 soc-glue@5f800000 { 378 compatible = "socionext,uniphier-ld11-soc-glue", 379 "simple-mfd", "syscon"; 380 reg = <0x5f800000 0x2000>; 381 382 pinctrl: pinctrl { 383 compatible = "socionext,uniphier-ld11-pinctrl"; 384 }; 385 }; 386 387 aidet: aidet@5fc20000 { 388 compatible = "socionext,uniphier-ld11-aidet"; 389 reg = <0x5fc20000 0x200>; 390 interrupt-controller; 391 #interrupt-cells = <2>; 392 }; 393 394 gic: interrupt-controller@5fe00000 { 395 compatible = "arm,gic-v3"; 396 reg = <0x5fe00000 0x10000>, /* GICD */ 397 <0x5fe40000 0x80000>; /* GICR */ 398 interrupt-controller; 399 #interrupt-cells = <3>; 400 interrupts = <1 9 4>; 401 }; 402 403 sysctrl@61840000 { 404 compatible = "socionext,uniphier-ld11-sysctrl", 405 "simple-mfd", "syscon"; 406 reg = <0x61840000 0x10000>; 407 408 sys_clk: clock { 409 compatible = "socionext,uniphier-ld11-clock"; 410 #clock-cells = <1>; 411 }; 412 413 sys_rst: reset { 414 compatible = "socionext,uniphier-ld11-reset"; 415 #reset-cells = <1>; 416 }; 417 418 watchdog { 419 compatible = "socionext,uniphier-wdt"; 420 }; 421 }; 422 423 nand: nand@68000000 { 424 compatible = "socionext,uniphier-denali-nand-v5b"; 425 status = "disabled"; 426 reg-names = "nand_data", "denali_reg"; 427 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 428 interrupts = <0 65 4>; 429 pinctrl-names = "default"; 430 pinctrl-0 = <&pinctrl_nand>; 431 clocks = <&sys_clk 2>; 432 }; 433 }; 434}; 435 436#include "uniphier-pinctrl.dtsi" 437