xref: /openbmc/u-boot/arch/arm/dts/uniphier-ld11.dtsi (revision 730d2544)
1/*
2 * Device Tree Source for UniPhier LD11 SoC
3 *
4 * Copyright (C) 2016 Socionext Inc.
5 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
6 *
7 * SPDX-License-Identifier:	GPL-2.0+	X11
8 */
9
10/memreserve/ 0x80000000 0x00000008;	/* cpu-release-addr */
11
12/ {
13	compatible = "socionext,uniphier-ld11";
14	#address-cells = <2>;
15	#size-cells = <2>;
16	interrupt-parent = <&gic>;
17
18	cpus {
19		#address-cells = <2>;
20		#size-cells = <0>;
21
22		cpu-map {
23			cluster0 {
24				core0 {
25					cpu = <&cpu0>;
26				};
27				core1 {
28					cpu = <&cpu1>;
29				};
30			};
31		};
32
33		cpu0: cpu@0 {
34			device_type = "cpu";
35			compatible = "arm,cortex-a53", "arm,armv8";
36			reg = <0 0x000>;
37			enable-method = "spin-table";
38			cpu-release-addr = <0 0x80000000>;
39		};
40
41		cpu1: cpu@1 {
42			device_type = "cpu";
43			compatible = "arm,cortex-a53", "arm,armv8";
44			reg = <0 0x001>;
45			enable-method = "spin-table";
46			cpu-release-addr = <0 0x80000000>;
47		};
48	};
49
50	clocks {
51		refclk: ref {
52			compatible = "fixed-clock";
53			#clock-cells = <0>;
54			clock-frequency = <25000000>;
55		};
56
57		i2c_clk: i2c_clk {
58			#clock-cells = <0>;
59			compatible = "fixed-clock";
60			clock-frequency = <50000000>;
61		};
62	};
63
64	timer {
65		compatible = "arm,armv8-timer";
66		interrupts = <1 13 4>,
67			     <1 14 4>,
68			     <1 11 4>,
69			     <1 10 4>;
70	};
71
72	soc {
73		compatible = "simple-bus";
74		#address-cells = <1>;
75		#size-cells = <1>;
76		ranges = <0 0 0 0xffffffff>;
77		u-boot,dm-pre-reloc;
78
79		serial0: serial@54006800 {
80			compatible = "socionext,uniphier-uart";
81			status = "disabled";
82			reg = <0x54006800 0x40>;
83			interrupts = <0 33 4>;
84			pinctrl-names = "default";
85			pinctrl-0 = <&pinctrl_uart0>;
86			clocks = <&peri_clk 0>;
87			clock-frequency = <58820000>;
88		};
89
90		serial1: serial@54006900 {
91			compatible = "socionext,uniphier-uart";
92			status = "disabled";
93			reg = <0x54006900 0x40>;
94			interrupts = <0 35 4>;
95			pinctrl-names = "default";
96			pinctrl-0 = <&pinctrl_uart1>;
97			clocks = <&peri_clk 1>;
98			clock-frequency = <58820000>;
99		};
100
101		serial2: serial@54006a00 {
102			compatible = "socionext,uniphier-uart";
103			status = "disabled";
104			reg = <0x54006a00 0x40>;
105			interrupts = <0 37 4>;
106			pinctrl-names = "default";
107			pinctrl-0 = <&pinctrl_uart2>;
108			clocks = <&peri_clk 2>;
109			clock-frequency = <58820000>;
110		};
111
112		serial3: serial@54006b00 {
113			compatible = "socionext,uniphier-uart";
114			status = "disabled";
115			reg = <0x54006b00 0x40>;
116			interrupts = <0 177 4>;
117			pinctrl-names = "default";
118			pinctrl-0 = <&pinctrl_uart3>;
119			clocks = <&peri_clk 3>;
120			clock-frequency = <58820000>;
121		};
122
123		i2c0: i2c@58780000 {
124			compatible = "socionext,uniphier-fi2c";
125			status = "disabled";
126			reg = <0x58780000 0x80>;
127			#address-cells = <1>;
128			#size-cells = <0>;
129			interrupts = <0 41 4>;
130			pinctrl-names = "default";
131			pinctrl-0 = <&pinctrl_i2c0>;
132			clocks = <&i2c_clk>;
133			clock-frequency = <100000>;
134		};
135
136		i2c1: i2c@58781000 {
137			compatible = "socionext,uniphier-fi2c";
138			status = "disabled";
139			reg = <0x58781000 0x80>;
140			#address-cells = <1>;
141			#size-cells = <0>;
142			interrupts = <0 42 4>;
143			pinctrl-names = "default";
144			pinctrl-0 = <&pinctrl_i2c1>;
145			clocks = <&i2c_clk>;
146			clock-frequency = <100000>;
147		};
148
149		i2c2: i2c@58782000 {
150			compatible = "socionext,uniphier-fi2c";
151			reg = <0x58782000 0x80>;
152			#address-cells = <1>;
153			#size-cells = <0>;
154			interrupts = <0 43 4>;
155			clocks = <&i2c_clk>;
156			clock-frequency = <400000>;
157		};
158
159		i2c3: i2c@58783000 {
160			compatible = "socionext,uniphier-fi2c";
161			status = "disabled";
162			reg = <0x58783000 0x80>;
163			#address-cells = <1>;
164			#size-cells = <0>;
165			interrupts = <0 44 4>;
166			pinctrl-names = "default";
167			pinctrl-0 = <&pinctrl_i2c3>;
168			clocks = <&i2c_clk>;
169			clock-frequency = <100000>;
170		};
171
172		i2c4: i2c@58784000 {
173			compatible = "socionext,uniphier-fi2c";
174			status = "disabled";
175			reg = <0x58784000 0x80>;
176			#address-cells = <1>;
177			#size-cells = <0>;
178			interrupts = <0 45 4>;
179			pinctrl-names = "default";
180			pinctrl-0 = <&pinctrl_i2c4>;
181			clocks = <&i2c_clk>;
182			clock-frequency = <100000>;
183		};
184
185		i2c5: i2c@58785000 {
186			compatible = "socionext,uniphier-fi2c";
187			reg = <0x58785000 0x80>;
188			#address-cells = <1>;
189			#size-cells = <0>;
190			interrupts = <0 25 4>;
191			clocks = <&i2c_clk>;
192			clock-frequency = <400000>;
193		};
194
195		system_bus: system-bus@58c00000 {
196			compatible = "socionext,uniphier-system-bus";
197			status = "disabled";
198			reg = <0x58c00000 0x400>;
199			#address-cells = <2>;
200			#size-cells = <1>;
201			pinctrl-names = "default";
202			pinctrl-0 = <&pinctrl_system_bus>;
203		};
204
205		smpctrl@59800000 {
206			compatible = "socionext,uniphier-smpctrl";
207			reg = <0x59801000 0x400>;
208		};
209
210		perictrl@59820000 {
211			compatible = "socionext,uniphier-perictrl",
212				     "simple-mfd", "syscon";
213			reg = <0x59820000 0x200>;
214
215			peri_clk: clock {
216				compatible = "socionext,uniphier-ld11-peri-clock";
217				#clock-cells = <1>;
218			};
219
220			peri_rst: reset {
221				compatible = "socionext,uniphier-ld11-peri-reset";
222				#reset-cells = <1>;
223			};
224		};
225
226		usb0: usb@5a800100 {
227			compatible = "socionext,uniphier-ehci", "generic-ehci";
228			status = "disabled";
229			reg = <0x5a800100 0x100>;
230			interrupts = <0 243 4>;
231			pinctrl-names = "default";
232			pinctrl-0 = <&pinctrl_usb0>;
233			clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>;
234			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
235				 <&mio_rst 12>;
236		};
237
238		usb1: usb@5a810100 {
239			compatible = "socionext,uniphier-ehci", "generic-ehci";
240			status = "disabled";
241			reg = <0x5a810100 0x100>;
242			interrupts = <0 244 4>;
243			pinctrl-names = "default";
244			pinctrl-0 = <&pinctrl_usb1>;
245			clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>;
246			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
247				 <&mio_rst 13>;
248		};
249
250		usb2: usb@5a820100 {
251			compatible = "socionext,uniphier-ehci", "generic-ehci";
252			status = "disabled";
253			reg = <0x5a820100 0x100>;
254			interrupts = <0 245 4>;
255			pinctrl-names = "default";
256			pinctrl-0 = <&pinctrl_usb2>;
257			clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>;
258			resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
259				 <&mio_rst 14>;
260		};
261
262		mioctrl@5b3e0000 {
263			compatible = "socionext,uniphier-mioctrl",
264				     "simple-mfd", "syscon";
265			reg = <0x5b3e0000 0x800>;
266
267			mio_clk: clock {
268				compatible = "socionext,uniphier-ld11-mio-clock";
269				#clock-cells = <1>;
270			};
271
272			mio_rst: reset {
273				compatible = "socionext,uniphier-ld11-mio-reset";
274				#reset-cells = <1>;
275				resets = <&sys_rst 7>;
276			};
277		};
278
279		soc-glue@5f800000 {
280			compatible = "socionext,uniphier-soc-glue",
281				     "simple-mfd", "syscon";
282			reg = <0x5f800000 0x2000>;
283			u-boot,dm-pre-reloc;
284
285			pinctrl: pinctrl {
286				compatible = "socionext,uniphier-ld11-pinctrl";
287				u-boot,dm-pre-reloc;
288			};
289		};
290
291		aidet@5fc20000 {
292			compatible = "simple-mfd", "syscon";
293			reg = <0x5fc20000 0x200>;
294		};
295
296		gic: interrupt-controller@5fe00000 {
297			compatible = "arm,gic-v3";
298			reg = <0x5fe00000 0x10000>,	/* GICD */
299			      <0x5fe40000 0x80000>;	/* GICR */
300			interrupt-controller;
301			#interrupt-cells = <3>;
302			interrupts = <1 9 4>;
303		};
304
305		sysctrl@61840000 {
306			compatible = "socionext,uniphier-ld11-sysctrl",
307				     "simple-mfd", "syscon";
308			reg = <0x61840000 0x4000>;
309
310			sys_clk: clock {
311				compatible = "socionext,uniphier-ld11-clock";
312				#clock-cells = <1>;
313			};
314
315			sys_rst: reset {
316				compatible = "socionext,uniphier-ld11-reset";
317				#reset-cells = <1>;
318			};
319		};
320	};
321};
322
323/include/ "uniphier-pinctrl.dtsi"
324