1/* 2 * Device Tree Source for UniPhier LD11 SoC 3 * 4 * Copyright (C) 2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ X11 8 */ 9 10/memreserve/ 0x80000000 0x00080000; 11 12/ { 13 compatible = "socionext,uniphier-ld11"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&gic>; 17 18 cpus { 19 #address-cells = <2>; 20 #size-cells = <0>; 21 22 cpu-map { 23 cluster0 { 24 core0 { 25 cpu = <&cpu0>; 26 }; 27 core1 { 28 cpu = <&cpu1>; 29 }; 30 }; 31 }; 32 33 cpu0: cpu@0 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53", "arm,armv8"; 36 reg = <0 0x000>; 37 clocks = <&sys_clk 33>; 38 enable-method = "psci"; 39 operating-points-v2 = <&cluster0_opp>; 40 }; 41 42 cpu1: cpu@1 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a53", "arm,armv8"; 45 reg = <0 0x001>; 46 clocks = <&sys_clk 33>; 47 enable-method = "psci"; 48 operating-points-v2 = <&cluster0_opp>; 49 }; 50 }; 51 52 cluster0_opp: opp_table { 53 compatible = "operating-points-v2"; 54 opp-shared; 55 56 opp@245000000 { 57 opp-hz = /bits/ 64 <245000000>; 58 clock-latency-ns = <300>; 59 }; 60 opp@250000000 { 61 opp-hz = /bits/ 64 <250000000>; 62 clock-latency-ns = <300>; 63 }; 64 opp@490000000 { 65 opp-hz = /bits/ 64 <490000000>; 66 clock-latency-ns = <300>; 67 }; 68 opp@500000000 { 69 opp-hz = /bits/ 64 <500000000>; 70 clock-latency-ns = <300>; 71 }; 72 opp@653334000 { 73 opp-hz = /bits/ 64 <653334000>; 74 clock-latency-ns = <300>; 75 }; 76 opp@666667000 { 77 opp-hz = /bits/ 64 <666667000>; 78 clock-latency-ns = <300>; 79 }; 80 opp@980000000 { 81 opp-hz = /bits/ 64 <980000000>; 82 clock-latency-ns = <300>; 83 }; 84 }; 85 86 psci { 87 compatible = "arm,psci-1.0"; 88 method = "smc"; 89 }; 90 91 clocks { 92 refclk: ref { 93 compatible = "fixed-clock"; 94 #clock-cells = <0>; 95 clock-frequency = <25000000>; 96 }; 97 }; 98 99 timer { 100 compatible = "arm,armv8-timer"; 101 interrupts = <1 13 4>, 102 <1 14 4>, 103 <1 11 4>, 104 <1 10 4>; 105 }; 106 107 soc { 108 compatible = "simple-bus"; 109 #address-cells = <1>; 110 #size-cells = <1>; 111 ranges = <0 0 0 0xffffffff>; 112 u-boot,dm-pre-reloc; 113 114 serial0: serial@54006800 { 115 compatible = "socionext,uniphier-uart"; 116 status = "disabled"; 117 reg = <0x54006800 0x40>; 118 interrupts = <0 33 4>; 119 pinctrl-names = "default"; 120 pinctrl-0 = <&pinctrl_uart0>; 121 clocks = <&peri_clk 0>; 122 clock-frequency = <58820000>; 123 }; 124 125 serial1: serial@54006900 { 126 compatible = "socionext,uniphier-uart"; 127 status = "disabled"; 128 reg = <0x54006900 0x40>; 129 interrupts = <0 35 4>; 130 pinctrl-names = "default"; 131 pinctrl-0 = <&pinctrl_uart1>; 132 clocks = <&peri_clk 1>; 133 clock-frequency = <58820000>; 134 }; 135 136 serial2: serial@54006a00 { 137 compatible = "socionext,uniphier-uart"; 138 status = "disabled"; 139 reg = <0x54006a00 0x40>; 140 interrupts = <0 37 4>; 141 pinctrl-names = "default"; 142 pinctrl-0 = <&pinctrl_uart2>; 143 clocks = <&peri_clk 2>; 144 clock-frequency = <58820000>; 145 }; 146 147 serial3: serial@54006b00 { 148 compatible = "socionext,uniphier-uart"; 149 status = "disabled"; 150 reg = <0x54006b00 0x40>; 151 interrupts = <0 177 4>; 152 pinctrl-names = "default"; 153 pinctrl-0 = <&pinctrl_uart3>; 154 clocks = <&peri_clk 3>; 155 clock-frequency = <58820000>; 156 }; 157 158 i2c0: i2c@58780000 { 159 compatible = "socionext,uniphier-fi2c"; 160 status = "disabled"; 161 reg = <0x58780000 0x80>; 162 #address-cells = <1>; 163 #size-cells = <0>; 164 interrupts = <0 41 4>; 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pinctrl_i2c0>; 167 clocks = <&peri_clk 4>; 168 clock-frequency = <100000>; 169 }; 170 171 i2c1: i2c@58781000 { 172 compatible = "socionext,uniphier-fi2c"; 173 status = "disabled"; 174 reg = <0x58781000 0x80>; 175 #address-cells = <1>; 176 #size-cells = <0>; 177 interrupts = <0 42 4>; 178 pinctrl-names = "default"; 179 pinctrl-0 = <&pinctrl_i2c1>; 180 clocks = <&peri_clk 5>; 181 clock-frequency = <100000>; 182 }; 183 184 i2c2: i2c@58782000 { 185 compatible = "socionext,uniphier-fi2c"; 186 reg = <0x58782000 0x80>; 187 #address-cells = <1>; 188 #size-cells = <0>; 189 interrupts = <0 43 4>; 190 clocks = <&peri_clk 6>; 191 clock-frequency = <400000>; 192 }; 193 194 i2c3: i2c@58783000 { 195 compatible = "socionext,uniphier-fi2c"; 196 status = "disabled"; 197 reg = <0x58783000 0x80>; 198 #address-cells = <1>; 199 #size-cells = <0>; 200 interrupts = <0 44 4>; 201 pinctrl-names = "default"; 202 pinctrl-0 = <&pinctrl_i2c3>; 203 clocks = <&peri_clk 7>; 204 clock-frequency = <100000>; 205 }; 206 207 i2c4: i2c@58784000 { 208 compatible = "socionext,uniphier-fi2c"; 209 status = "disabled"; 210 reg = <0x58784000 0x80>; 211 #address-cells = <1>; 212 #size-cells = <0>; 213 interrupts = <0 45 4>; 214 pinctrl-names = "default"; 215 pinctrl-0 = <&pinctrl_i2c4>; 216 clocks = <&peri_clk 8>; 217 clock-frequency = <100000>; 218 }; 219 220 i2c5: i2c@58785000 { 221 compatible = "socionext,uniphier-fi2c"; 222 reg = <0x58785000 0x80>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 interrupts = <0 25 4>; 226 clocks = <&peri_clk 9>; 227 clock-frequency = <400000>; 228 }; 229 230 system_bus: system-bus@58c00000 { 231 compatible = "socionext,uniphier-system-bus"; 232 status = "disabled"; 233 reg = <0x58c00000 0x400>; 234 #address-cells = <2>; 235 #size-cells = <1>; 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_system_bus>; 238 }; 239 240 smpctrl@59800000 { 241 compatible = "socionext,uniphier-smpctrl"; 242 reg = <0x59801000 0x400>; 243 }; 244 245 sdctrl@59810000 { 246 compatible = "socionext,uniphier-ld11-sdctrl", 247 "simple-mfd", "syscon"; 248 reg = <0x59810000 0x400>; 249 250 sd_rst: reset { 251 compatible = "socionext,uniphier-ld11-sd-reset"; 252 #reset-cells = <1>; 253 }; 254 }; 255 256 perictrl@59820000 { 257 compatible = "socionext,uniphier-ld11-perictrl", 258 "simple-mfd", "syscon"; 259 reg = <0x59820000 0x200>; 260 261 peri_clk: clock { 262 compatible = "socionext,uniphier-ld11-peri-clock"; 263 #clock-cells = <1>; 264 }; 265 266 peri_rst: reset { 267 compatible = "socionext,uniphier-ld11-peri-reset"; 268 #reset-cells = <1>; 269 }; 270 }; 271 272 emmc: sdhc@5a000000 { 273 compatible = "cdns,sd4hc"; 274 reg = <0x5a000000 0x400>; 275 interrupts = <0 78 4>; 276 pinctrl-names = "default"; 277 pinctrl-0 = <&pinctrl_emmc_1v8>; 278 clocks = <&sys_clk 4>; 279 bus-width = <8>; 280 mmc-ddr-1_8v; 281 mmc-hs200-1_8v; 282 /* mmc-hs400-1_8v; support depends on board design */ 283 }; 284 285 usb0: usb@5a800100 { 286 compatible = "socionext,uniphier-ehci", "generic-ehci"; 287 status = "disabled"; 288 reg = <0x5a800100 0x100>; 289 interrupts = <0 243 4>; 290 pinctrl-names = "default"; 291 pinctrl-0 = <&pinctrl_usb0>; 292 clocks = <&mio_clk 7>, <&mio_clk 8>, <&mio_clk 12>; 293 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 294 <&mio_rst 12>; 295 }; 296 297 usb1: usb@5a810100 { 298 compatible = "socionext,uniphier-ehci", "generic-ehci"; 299 status = "disabled"; 300 reg = <0x5a810100 0x100>; 301 interrupts = <0 244 4>; 302 pinctrl-names = "default"; 303 pinctrl-0 = <&pinctrl_usb1>; 304 clocks = <&mio_clk 7>, <&mio_clk 9>, <&mio_clk 13>; 305 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 306 <&mio_rst 13>; 307 }; 308 309 usb2: usb@5a820100 { 310 compatible = "socionext,uniphier-ehci", "generic-ehci"; 311 status = "disabled"; 312 reg = <0x5a820100 0x100>; 313 interrupts = <0 245 4>; 314 pinctrl-names = "default"; 315 pinctrl-0 = <&pinctrl_usb2>; 316 clocks = <&mio_clk 7>, <&mio_clk 10>, <&mio_clk 14>; 317 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, 318 <&mio_rst 14>; 319 }; 320 321 mioctrl@5b3e0000 { 322 compatible = "socionext,uniphier-mioctrl", 323 "simple-mfd", "syscon"; 324 reg = <0x5b3e0000 0x800>; 325 326 mio_clk: clock { 327 compatible = "socionext,uniphier-ld11-mio-clock"; 328 #clock-cells = <1>; 329 }; 330 331 mio_rst: reset { 332 compatible = "socionext,uniphier-ld11-mio-reset"; 333 #reset-cells = <1>; 334 resets = <&sys_rst 7>; 335 }; 336 }; 337 338 soc-glue@5f800000 { 339 compatible = "socionext,uniphier-ld11-soc-glue", 340 "simple-mfd", "syscon"; 341 reg = <0x5f800000 0x2000>; 342 u-boot,dm-pre-reloc; 343 344 pinctrl: pinctrl { 345 compatible = "socionext,uniphier-ld11-pinctrl"; 346 u-boot,dm-pre-reloc; 347 }; 348 }; 349 350 aidet@5fc20000 { 351 compatible = "simple-mfd", "syscon"; 352 reg = <0x5fc20000 0x200>; 353 }; 354 355 gic: interrupt-controller@5fe00000 { 356 compatible = "arm,gic-v3"; 357 reg = <0x5fe00000 0x10000>, /* GICD */ 358 <0x5fe40000 0x80000>; /* GICR */ 359 interrupt-controller; 360 #interrupt-cells = <3>; 361 interrupts = <1 9 4>; 362 }; 363 364 sysctrl@61840000 { 365 compatible = "socionext,uniphier-ld11-sysctrl", 366 "simple-mfd", "syscon"; 367 reg = <0x61840000 0x10000>; 368 369 sys_clk: clock { 370 compatible = "socionext,uniphier-ld11-clock"; 371 #clock-cells = <1>; 372 }; 373 374 sys_rst: reset { 375 compatible = "socionext,uniphier-ld11-reset"; 376 #reset-cells = <1>; 377 }; 378 }; 379 380 nand: nand@68000000 { 381 compatible = "socionext,denali-nand-v5b"; 382 status = "disabled"; 383 reg-names = "nand_data", "denali_reg"; 384 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 385 interrupts = <0 65 4>; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&pinctrl_nand>; 388 clocks = <&sys_clk 2>; 389 nand-ecc-strength = <8>; 390 }; 391 }; 392}; 393 394/include/ "uniphier-pinctrl.dtsi" 395