1/* 2 * Device Tree Source for UniPhier LD11 SoC 3 * 4 * Copyright (C) 2016 Socionext Inc. 5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 6 * 7 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/gpio/uniphier-gpio.h> 12 13/memreserve/ 0x80000000 0x02000000; 14 15/ { 16 compatible = "socionext,uniphier-ld11"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 interrupt-parent = <&gic>; 20 21 cpus { 22 #address-cells = <2>; 23 #size-cells = <0>; 24 25 cpu-map { 26 cluster0 { 27 core0 { 28 cpu = <&cpu0>; 29 }; 30 core1 { 31 cpu = <&cpu1>; 32 }; 33 }; 34 }; 35 36 cpu0: cpu@0 { 37 device_type = "cpu"; 38 compatible = "arm,cortex-a53", "arm,armv8"; 39 reg = <0 0x000>; 40 clocks = <&sys_clk 33>; 41 enable-method = "psci"; 42 operating-points-v2 = <&cluster0_opp>; 43 }; 44 45 cpu1: cpu@1 { 46 device_type = "cpu"; 47 compatible = "arm,cortex-a53", "arm,armv8"; 48 reg = <0 0x001>; 49 clocks = <&sys_clk 33>; 50 enable-method = "psci"; 51 operating-points-v2 = <&cluster0_opp>; 52 }; 53 }; 54 55 cluster0_opp: opp-table { 56 compatible = "operating-points-v2"; 57 opp-shared; 58 59 opp-245000000 { 60 opp-hz = /bits/ 64 <245000000>; 61 clock-latency-ns = <300>; 62 }; 63 opp-250000000 { 64 opp-hz = /bits/ 64 <250000000>; 65 clock-latency-ns = <300>; 66 }; 67 opp-490000000 { 68 opp-hz = /bits/ 64 <490000000>; 69 clock-latency-ns = <300>; 70 }; 71 opp-500000000 { 72 opp-hz = /bits/ 64 <500000000>; 73 clock-latency-ns = <300>; 74 }; 75 opp-653334000 { 76 opp-hz = /bits/ 64 <653334000>; 77 clock-latency-ns = <300>; 78 }; 79 opp-666667000 { 80 opp-hz = /bits/ 64 <666667000>; 81 clock-latency-ns = <300>; 82 }; 83 opp-980000000 { 84 opp-hz = /bits/ 64 <980000000>; 85 clock-latency-ns = <300>; 86 }; 87 }; 88 89 psci { 90 compatible = "arm,psci-1.0"; 91 method = "smc"; 92 }; 93 94 clocks { 95 refclk: ref { 96 compatible = "fixed-clock"; 97 #clock-cells = <0>; 98 clock-frequency = <25000000>; 99 }; 100 }; 101 102 emmc_pwrseq: emmc-pwrseq { 103 compatible = "mmc-pwrseq-emmc"; 104 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>; 105 }; 106 107 timer { 108 compatible = "arm,armv8-timer"; 109 interrupts = <1 13 4>, 110 <1 14 4>, 111 <1 11 4>, 112 <1 10 4>; 113 }; 114 115 soc@0 { 116 compatible = "simple-bus"; 117 #address-cells = <1>; 118 #size-cells = <1>; 119 ranges = <0 0 0 0xffffffff>; 120 121 serial0: serial@54006800 { 122 compatible = "socionext,uniphier-uart"; 123 status = "disabled"; 124 reg = <0x54006800 0x40>; 125 interrupts = <0 33 4>; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pinctrl_uart0>; 128 clocks = <&peri_clk 0>; 129 clock-frequency = <58820000>; 130 resets = <&peri_rst 0>; 131 }; 132 133 serial1: serial@54006900 { 134 compatible = "socionext,uniphier-uart"; 135 status = "disabled"; 136 reg = <0x54006900 0x40>; 137 interrupts = <0 35 4>; 138 pinctrl-names = "default"; 139 pinctrl-0 = <&pinctrl_uart1>; 140 clocks = <&peri_clk 1>; 141 clock-frequency = <58820000>; 142 resets = <&peri_rst 1>; 143 }; 144 145 serial2: serial@54006a00 { 146 compatible = "socionext,uniphier-uart"; 147 status = "disabled"; 148 reg = <0x54006a00 0x40>; 149 interrupts = <0 37 4>; 150 pinctrl-names = "default"; 151 pinctrl-0 = <&pinctrl_uart2>; 152 clocks = <&peri_clk 2>; 153 clock-frequency = <58820000>; 154 resets = <&peri_rst 2>; 155 }; 156 157 serial3: serial@54006b00 { 158 compatible = "socionext,uniphier-uart"; 159 status = "disabled"; 160 reg = <0x54006b00 0x40>; 161 interrupts = <0 177 4>; 162 pinctrl-names = "default"; 163 pinctrl-0 = <&pinctrl_uart3>; 164 clocks = <&peri_clk 3>; 165 clock-frequency = <58820000>; 166 resets = <&peri_rst 3>; 167 }; 168 169 gpio: gpio@55000000 { 170 compatible = "socionext,uniphier-gpio"; 171 reg = <0x55000000 0x200>; 172 interrupt-parent = <&aidet>; 173 interrupt-controller; 174 #interrupt-cells = <2>; 175 gpio-controller; 176 #gpio-cells = <2>; 177 gpio-ranges = <&pinctrl 0 0 0>, 178 <&pinctrl 43 0 0>, 179 <&pinctrl 51 0 0>, 180 <&pinctrl 96 0 0>, 181 <&pinctrl 160 0 0>, 182 <&pinctrl 184 0 0>; 183 gpio-ranges-group-names = "gpio_range0", 184 "gpio_range1", 185 "gpio_range2", 186 "gpio_range3", 187 "gpio_range4", 188 "gpio_range5"; 189 ngpios = <200>; 190 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 191 <21 217 3>; 192 }; 193 194 adamv@57920000 { 195 compatible = "socionext,uniphier-ld11-adamv", 196 "simple-mfd", "syscon"; 197 reg = <0x57920000 0x1000>; 198 199 adamv_rst: reset { 200 compatible = "socionext,uniphier-ld11-adamv-reset"; 201 #reset-cells = <1>; 202 }; 203 }; 204 205 i2c0: i2c@58780000 { 206 compatible = "socionext,uniphier-fi2c"; 207 status = "disabled"; 208 reg = <0x58780000 0x80>; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 interrupts = <0 41 4>; 212 pinctrl-names = "default"; 213 pinctrl-0 = <&pinctrl_i2c0>; 214 clocks = <&peri_clk 4>; 215 resets = <&peri_rst 4>; 216 clock-frequency = <100000>; 217 }; 218 219 i2c1: i2c@58781000 { 220 compatible = "socionext,uniphier-fi2c"; 221 status = "disabled"; 222 reg = <0x58781000 0x80>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 interrupts = <0 42 4>; 226 pinctrl-names = "default"; 227 pinctrl-0 = <&pinctrl_i2c1>; 228 clocks = <&peri_clk 5>; 229 resets = <&peri_rst 5>; 230 clock-frequency = <100000>; 231 }; 232 233 i2c2: i2c@58782000 { 234 compatible = "socionext,uniphier-fi2c"; 235 reg = <0x58782000 0x80>; 236 #address-cells = <1>; 237 #size-cells = <0>; 238 interrupts = <0 43 4>; 239 clocks = <&peri_clk 6>; 240 resets = <&peri_rst 6>; 241 clock-frequency = <400000>; 242 }; 243 244 i2c3: i2c@58783000 { 245 compatible = "socionext,uniphier-fi2c"; 246 status = "disabled"; 247 reg = <0x58783000 0x80>; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 interrupts = <0 44 4>; 251 pinctrl-names = "default"; 252 pinctrl-0 = <&pinctrl_i2c3>; 253 clocks = <&peri_clk 7>; 254 resets = <&peri_rst 7>; 255 clock-frequency = <100000>; 256 }; 257 258 i2c4: i2c@58784000 { 259 compatible = "socionext,uniphier-fi2c"; 260 status = "disabled"; 261 reg = <0x58784000 0x80>; 262 #address-cells = <1>; 263 #size-cells = <0>; 264 interrupts = <0 45 4>; 265 pinctrl-names = "default"; 266 pinctrl-0 = <&pinctrl_i2c4>; 267 clocks = <&peri_clk 8>; 268 resets = <&peri_rst 8>; 269 clock-frequency = <100000>; 270 }; 271 272 i2c5: i2c@58785000 { 273 compatible = "socionext,uniphier-fi2c"; 274 reg = <0x58785000 0x80>; 275 #address-cells = <1>; 276 #size-cells = <0>; 277 interrupts = <0 25 4>; 278 clocks = <&peri_clk 9>; 279 resets = <&peri_rst 9>; 280 clock-frequency = <400000>; 281 }; 282 283 system_bus: system-bus@58c00000 { 284 compatible = "socionext,uniphier-system-bus"; 285 status = "disabled"; 286 reg = <0x58c00000 0x400>; 287 #address-cells = <2>; 288 #size-cells = <1>; 289 pinctrl-names = "default"; 290 pinctrl-0 = <&pinctrl_system_bus>; 291 }; 292 293 smpctrl@59801000 { 294 compatible = "socionext,uniphier-smpctrl"; 295 reg = <0x59801000 0x400>; 296 }; 297 298 sdctrl@59810000 { 299 compatible = "socionext,uniphier-ld11-sdctrl", 300 "simple-mfd", "syscon"; 301 reg = <0x59810000 0x400>; 302 303 sd_rst: reset { 304 compatible = "socionext,uniphier-ld11-sd-reset"; 305 #reset-cells = <1>; 306 }; 307 }; 308 309 perictrl@59820000 { 310 compatible = "socionext,uniphier-ld11-perictrl", 311 "simple-mfd", "syscon"; 312 reg = <0x59820000 0x200>; 313 314 peri_clk: clock { 315 compatible = "socionext,uniphier-ld11-peri-clock"; 316 #clock-cells = <1>; 317 }; 318 319 peri_rst: reset { 320 compatible = "socionext,uniphier-ld11-peri-reset"; 321 #reset-cells = <1>; 322 }; 323 }; 324 325 emmc: sdhc@5a000000 { 326 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 327 reg = <0x5a000000 0x400>; 328 interrupts = <0 78 4>; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&pinctrl_emmc_1v8>; 331 clocks = <&sys_clk 4>; 332 resets = <&sys_rst 4>; 333 bus-width = <8>; 334 mmc-ddr-1_8v; 335 mmc-hs200-1_8v; 336 mmc-pwrseq = <&emmc_pwrseq>; 337 cdns,phy-input-delay-legacy = <4>; 338 cdns,phy-input-delay-mmc-highspeed = <2>; 339 cdns,phy-input-delay-mmc-ddr = <3>; 340 cdns,phy-dll-delay-sdclk = <21>; 341 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 342 }; 343 344 usb0: usb@5a800100 { 345 compatible = "socionext,uniphier-ehci", "generic-ehci"; 346 status = "disabled"; 347 reg = <0x5a800100 0x100>; 348 interrupts = <0 243 4>; 349 pinctrl-names = "default"; 350 pinctrl-0 = <&pinctrl_usb0>; 351 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, 352 <&mio_clk 12>; 353 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 354 <&mio_rst 12>; 355 }; 356 357 usb1: usb@5a810100 { 358 compatible = "socionext,uniphier-ehci", "generic-ehci"; 359 status = "disabled"; 360 reg = <0x5a810100 0x100>; 361 interrupts = <0 244 4>; 362 pinctrl-names = "default"; 363 pinctrl-0 = <&pinctrl_usb1>; 364 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, 365 <&mio_clk 13>; 366 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 367 <&mio_rst 13>; 368 }; 369 370 usb2: usb@5a820100 { 371 compatible = "socionext,uniphier-ehci", "generic-ehci"; 372 status = "disabled"; 373 reg = <0x5a820100 0x100>; 374 interrupts = <0 245 4>; 375 pinctrl-names = "default"; 376 pinctrl-0 = <&pinctrl_usb2>; 377 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, 378 <&mio_clk 14>; 379 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, 380 <&mio_rst 14>; 381 }; 382 383 mioctrl@5b3e0000 { 384 compatible = "socionext,uniphier-ld11-mioctrl", 385 "simple-mfd", "syscon"; 386 reg = <0x5b3e0000 0x800>; 387 388 mio_clk: clock { 389 compatible = "socionext,uniphier-ld11-mio-clock"; 390 #clock-cells = <1>; 391 }; 392 393 mio_rst: reset { 394 compatible = "socionext,uniphier-ld11-mio-reset"; 395 #reset-cells = <1>; 396 resets = <&sys_rst 7>; 397 }; 398 }; 399 400 soc-glue@5f800000 { 401 compatible = "socionext,uniphier-ld11-soc-glue", 402 "simple-mfd", "syscon"; 403 reg = <0x5f800000 0x2000>; 404 405 pinctrl: pinctrl { 406 compatible = "socionext,uniphier-ld11-pinctrl"; 407 }; 408 }; 409 410 soc-glue@5f900000 { 411 compatible = "socionext,uniphier-ld11-soc-glue-debug", 412 "simple-mfd"; 413 #address-cells = <1>; 414 #size-cells = <1>; 415 ranges = <0 0x5f900000 0x2000>; 416 417 efuse@100 { 418 compatible = "socionext,uniphier-efuse"; 419 reg = <0x100 0x28>; 420 }; 421 422 efuse@200 { 423 compatible = "socionext,uniphier-efuse"; 424 reg = <0x200 0x68>; 425 }; 426 }; 427 428 aidet: aidet@5fc20000 { 429 compatible = "socionext,uniphier-ld11-aidet"; 430 reg = <0x5fc20000 0x200>; 431 interrupt-controller; 432 #interrupt-cells = <2>; 433 }; 434 435 gic: interrupt-controller@5fe00000 { 436 compatible = "arm,gic-v3"; 437 reg = <0x5fe00000 0x10000>, /* GICD */ 438 <0x5fe40000 0x80000>; /* GICR */ 439 interrupt-controller; 440 #interrupt-cells = <3>; 441 interrupts = <1 9 4>; 442 }; 443 444 sysctrl@61840000 { 445 compatible = "socionext,uniphier-ld11-sysctrl", 446 "simple-mfd", "syscon"; 447 reg = <0x61840000 0x10000>; 448 449 sys_clk: clock { 450 compatible = "socionext,uniphier-ld11-clock"; 451 #clock-cells = <1>; 452 }; 453 454 sys_rst: reset { 455 compatible = "socionext,uniphier-ld11-reset"; 456 #reset-cells = <1>; 457 }; 458 459 watchdog { 460 compatible = "socionext,uniphier-wdt"; 461 }; 462 }; 463 464 nand: nand@68000000 { 465 compatible = "socionext,uniphier-denali-nand-v5b"; 466 status = "disabled"; 467 reg-names = "nand_data", "denali_reg"; 468 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 469 interrupts = <0 65 4>; 470 pinctrl-names = "default"; 471 pinctrl-0 = <&pinctrl_nand>; 472 clocks = <&sys_clk 2>; 473 resets = <&sys_rst 2>; 474 }; 475 }; 476}; 477 478#include "uniphier-pinctrl.dtsi" 479