xref: /openbmc/u-boot/arch/arm/dts/tegra30.dtsi (revision 63495ad7)
1#include "skeleton.dtsi"
2
3/ {
4	compatible = "nvidia,tegra30";
5
6	tegra_car: clock {
7		compatible = "nvidia,tegra30-car";
8		reg = <0x60006000 0x1000>;
9		#clock-cells = <1>;
10	};
11
12	apbdma: dma {
13		compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
14		reg = <0x6000a000 0x1400>;
15		interrupts = <0 104 0x04
16			      0 105 0x04
17			      0 106 0x04
18			      0 107 0x04
19			      0 108 0x04
20			      0 109 0x04
21			      0 110 0x04
22			      0 111 0x04
23			      0 112 0x04
24			      0 113 0x04
25			      0 114 0x04
26			      0 115 0x04
27			      0 116 0x04
28			      0 117 0x04
29			      0 118 0x04
30			      0 119 0x04
31			      0 128 0x04
32			      0 129 0x04
33			      0 130 0x04
34			      0 131 0x04
35			      0 132 0x04
36			      0 133 0x04
37			      0 134 0x04
38			      0 135 0x04
39			      0 136 0x04
40			      0 137 0x04
41			      0 138 0x04
42			      0 139 0x04
43			      0 140 0x04
44			      0 141 0x04
45			      0 142 0x04
46			      0 143 0x04>;
47		clocks = <&tegra_car 34>;
48	};
49
50	gpio: gpio {
51		compatible = "nvidia,tegra30-gpio";
52		reg = <0x6000d000 0x1000>;
53		interrupts = <0 32 0x04
54			      0 33 0x04
55			      0 34 0x04
56			      0 35 0x04
57			      0 55 0x04
58			      0 87 0x04
59			      0 89 0x04
60			      0 125 0x04>;
61		#gpio-cells = <2>;
62		gpio-controller;
63		#interrupt-cells = <2>;
64		interrupt-controller;
65	};
66
67	i2c@7000c000 {
68		compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
69		reg = <0x7000c000 0x100>;
70		interrupts = <0 38 0x04>;
71		#address-cells = <1>;
72		#size-cells = <0>;
73		clocks = <&tegra_car 12>, <&tegra_car 182>;
74		clock-names = "div-clk", "fast-clk";
75		status = "disabled";
76	};
77
78	i2c@7000c400 {
79		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
80		reg = <0x7000c400 0x100>;
81		interrupts = <0 84 0x04>;
82		#address-cells = <1>;
83		#size-cells = <0>;
84		clocks = <&tegra_car 54>, <&tegra_car 182>;
85		clock-names = "div-clk", "fast-clk";
86		status = "disabled";
87	};
88
89	i2c@7000c500 {
90		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
91		reg = <0x7000c500 0x100>;
92		interrupts = <0 92 0x04>;
93		#address-cells = <1>;
94		#size-cells = <0>;
95		clocks = <&tegra_car 67>, <&tegra_car 182>;
96		clock-names = "div-clk", "fast-clk";
97		status = "disabled";
98	};
99
100	i2c@7000c700 {
101		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
102		reg = <0x7000c700 0x100>;
103		interrupts = <0 120 0x04>;
104		#address-cells = <1>;
105		#size-cells = <0>;
106		clocks = <&tegra_car 103>, <&tegra_car 182>;
107		clock-names = "div-clk", "fast-clk";
108		status = "disabled";
109	};
110
111	i2c@7000d000 {
112		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
113		reg = <0x7000d000 0x100>;
114		interrupts = <0 53 0x04>;
115		#address-cells = <1>;
116		#size-cells = <0>;
117		clocks = <&tegra_car 47>, <&tegra_car 182>;
118		clock-names = "div-clk", "fast-clk";
119		status = "disabled";
120	};
121
122	spi@7000d400 {
123		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
124		reg = <0x7000d400 0x200>;
125		interrupts = <0 59 0x04>;
126		nvidia,dma-request-selector = <&apbdma 15>;
127		#address-cells = <1>;
128		#size-cells = <0>;
129		clocks = <&tegra_car 41>;
130		status = "disabled";
131	};
132
133	spi@7000d600 {
134		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
135		reg = <0x7000d600 0x200>;
136		interrupts = <0 82 0x04>;
137		nvidia,dma-request-selector = <&apbdma 16>;
138		#address-cells = <1>;
139		#size-cells = <0>;
140		clocks = <&tegra_car 44>;
141		status = "disabled";
142	};
143
144	spi@7000d800 {
145		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
146		reg = <0x7000d480 0x200>;
147		interrupts = <0 83 0x04>;
148		nvidia,dma-request-selector = <&apbdma 17>;
149		#address-cells = <1>;
150		#size-cells = <0>;
151		clocks = <&tegra_car 46>;
152		status = "disabled";
153	};
154
155	spi@7000da00 {
156		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
157		reg = <0x7000da00 0x200>;
158		interrupts = <0 93 0x04>;
159		nvidia,dma-request-selector = <&apbdma 18>;
160		#address-cells = <1>;
161		#size-cells = <0>;
162		clocks = <&tegra_car 68>;
163		status = "disabled";
164	};
165
166	spi@7000dc00 {
167		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
168		reg = <0x7000dc00 0x200>;
169		interrupts = <0 94 0x04>;
170		nvidia,dma-request-selector = <&apbdma 27>;
171		#address-cells = <1>;
172		#size-cells = <0>;
173		clocks = <&tegra_car 104>;
174		status = "disabled";
175	};
176
177	spi@7000de00 {
178		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
179		reg = <0x7000de00 0x200>;
180		interrupts = <0 79 0x04>;
181		nvidia,dma-request-selector = <&apbdma 28>;
182		#address-cells = <1>;
183		#size-cells = <0>;
184		clocks = <&tegra_car 105>;
185		status = "disabled";
186	};
187
188	sdhci@78000000 {
189		compatible = "nvidia,tegra30-sdhci";
190		reg = <0x78000000 0x200>;
191		interrupts = <0 14 0x04>;
192		clocks = <&tegra_car 14>;
193		status = "disabled";
194	};
195
196	sdhci@78000200 {
197		compatible = "nvidia,tegra30-sdhci";
198		reg = <0x78000200 0x200>;
199		interrupts = <0 15 0x04>;
200		clocks = <&tegra_car 9>;
201		status = "disabled";
202	};
203
204	sdhci@78000400 {
205		compatible = "nvidia,tegra30-sdhci";
206		reg = <0x78000400 0x200>;
207		interrupts = <0 19 0x04>;
208		clocks = <&tegra_car 69>;
209		status = "disabled";
210	};
211
212	sdhci@78000600 {
213		compatible = "nvidia,tegra30-sdhci";
214		reg = <0x78000600 0x200>;
215		interrupts = <0 31 0x04>;
216		clocks = <&tegra_car 15>;
217		status = "disabled";
218	};
219};
220